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1 for more information www.linear.com/ltm4675 typical application features description dual 9a or single 18a module regulator with digital power system management the lt m ? 4675 is a dual 9a or single 18a step-down module ? (micromodule) dc/dc regulator with 70ms turn - on time . it features remote configurability and telemetry -monitoring of power management parameters over pmbus an open standard i 2 c - based digital interface protocol . the ltm4675 is comprised of fast analog control loops, precision mixed-signal circuitry , eeprom, power mosfets , inductors and supporting components. the ltm 4675 s 2- wire serial interface allows outputs to be margined , tuned and ramped up and down at programmable slew rates with sequencing delay times. input and output currents and voltages, output power, temperatures , uptime and peak values are readable. custom configuration of the eeprom contents is not required. at start-up, output voltages, switching frequency, and channel phase angle assignments can be set by pin-strapping resistors. the ltpowerplay ? gui and dc 1613 usb - to - pmbus converter and demo kits are available. the ltm4675 is offered in a 16mm 11.9mm 3.51mm bga package available with snpb or rohs compliant terminal finish. applications n dual, fast, analog loops with digital interface for control and monitoring n wide input voltage range: 4.5v to 17v n output voltage range: 0.5v to 5.5v n 0.5% maximum dc output error over temperature n 2.5% current readback accuracy at 9a load n 400khz pmbus-compliant i 2 c serial interface n integrated 16-bit ? adc n supports telemetry polling rates up to 125hz n constant frequency current mode control n parallel and current share multiple modules n all 7-bit slave addresses supported n drop-in pin-compatible to dual 13a ltm4676a n 16mm 11.9mm 3.51mm bga package readable data: n input and output voltages, currents, and temperatures n running peak values, uptime, faults and warnings n onboard eeprom fault log record writable data and configurable parameters: n output voltage, voltage sequencing and margining n digital soft-start/stop ramp n ov/uv/ot, uvlo, frequency and phasing n system optimization, characterization and data min- ing in prototype, production and field environments l, lt , lt c , lt m , linear technology, the linear logo, module and polyphase are registered trademarks and ltpowerplay is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 7420359, 8163643. licensed under u.s. patent 7000125 and other related patents worldwide. dual 9a module regulator with digital interface for control and monitoring* using pmbus and ltpowerplay to monitor telemetry and margin v out0 /v out1 during load pattern tests. 10hz polling rate. 12v in 22f 2 on/off control fault interrupts, power sequencing pwm clock and time-base synchronization v in 5.75v to 17v v osns0 ? v out0 , adjustable up to 9a 100f 4 v osns0 + v out0 v in0 v in1 sv in load 0 v out1 , adjustable up to 9a 100f 4 i 2 c/smbus i/f with pmbus command set to/from ipmi or other board management controller load 1 run 0 run 1 wp *for complete circuit, see figure 60 ltm4675 gnd 4675 ta01a sgnd scl sda alert v osns1 v out1 gpio 0 gpio 1 register write protection sync share_clk 1.1 1.0 0.9 v out0 (v) v out1 (v) 0.8 1.9 1.8 1.7 1.6 0 3 6 time (s) output voltage readback, v out margined 7.5% low 4675 ta01b 9 12 10 5 i out0 (a) i out1 (a) 0 10 5 0 0 3 6 time (s) output current readback, varying load pattern 4675 ta01c 9 12 1.0 0.5 i in0 (a) i in1 (a) 0 2.0 1.0 0 0 3 6 time (s) input current readback 4675 ta01d 9 12 60 57 54 channel 0 temp (c) channel 1 temp (c) 51 60 57 54 51 0 3 6 time (sec) power stage temperature readback 4675 ta01e 9 12 click to view associated video design idea. ltm 4675 4675f
2 for more information www.linear.com/ltm4675 table of contents features ..................................................... 1 applications ................................................ 1 typical application ........................................ 1 description .................................................. 1 absolute maximum ratings .............................. 3 order information .......................................... 3 pin configuration .......................................... 3 electrical characteristics ................................. 4 typical performance characteristics .................. 11 pin functions .............................................. 13 simplified block diagram ............................... 18 decoupling requirements ............................... 18 functional diagram ...................................... 19 test circuits ............................................... 20 operation ................................................... 21 power module introduction ......................................... 21 power module configurability and readback data ........................................................ 23 time-averaged and peak readback data .................... 25 power module overview ............................................. 28 eeprom ..................................................................... 32 serial interface ............................................................ 33 device addressing ...................................................... 33 fault detection and handling ...................................... 34 responses to v out and i out faults ............................. 35 responses to timing faults ........................................ 36 responses to sv in ov faults ...................................... 36 responses to ot/ut faults ......................................... 36 responses to external faults ..................................... 36 fault logging .............................................................. 37 bus timeout protection .............................................. 37 pmbus command summary ............................ 38 pmbus commands .................................................... 38 v in to v out step-down ratios .................................... 48 input capacitors .......................................................... 48 output capacitors ....................................................... 48 light load current operation ...................................... 48 switching frequency and phase ................................. 49 minimum on-time considerations .............................. 51 variable delay time, soft-start and output voltage ramping ................................................................. 51 digital servo mode ..................................................... 52 soft off (sequenced off) ............................................ 53 undervoltage lockout ................................................. 53 fault detection and handling ...................................... 54 open-drain pins .......................................................... 54 phase-locked loop and frequency synchronization .. 55 rconfig pin-straps (external resistor configuration pins) ................................................. 56 voltage selection ........................................................ 56 connecting the usb to the i 2 c/smbus/pmbus controller to the ltm4675 in system ..................... 56 ltpowerplay: an interactive gui for digital power system management .............................................. 60 pmbus communication and command processing .... 61 thermal considerations and output current derating ......................................... 62 emi performance ........................................................ 69 safety considerations ................................................. 69 layout checklist/example ........................................... 69 typical applications ...................................... 71 appendix a ................................................. 77 similarity between pmbus, smbus and i 2 c 2-wire interface ...................................................... 77 appendix b ................................................. 78 pmbus serial digital interface .................................... 78 appendix c: pmbus command details ................ 82 addressing and write protect ..................................... 82 general configuration registers ................................. 84 on/off/margin ............................................................. 85 pwm config ............................................................... 87 voltage ........................................................................ 89 current ........................................................................ 92 temperature ................................................................ 95 timing ......................................................................... 97 fault response ........................................................... 99 fault sharing ............................................................. 106 scratchpad ................................................................ 108 identification ............................................................. 108 fault warning and status .......................................... 109 telemetry .................................................................. 116 nvm (eeprom) memory commands ....................... 119 package description ................................... 125 package photograph ................................... 126 package description ................................... 127 typical application ..................................... 128 design resources ...................................... 128 related parts ............................................ 128 ltm 4675 4675f
3 for more information www.linear.com/ltm4675 pin configuration absolute maximum ratings terminal voltages : v in n ( note 4), sv in ..................................... C0.3 v to 20 v v out n ........................................................... C0.3 v to 6 v v osns 0 + , v orb 0 + , v osns 1 , v orb 1 , intv cc .... C0.3 v to 6 v run n , sda , scl , alert ........................... C0.3 v to 5.5 v f swphcfg , v out n cfg , v trim n cfg , asel .. C0.3 v to 2.75 v v dd 33 , gpio n , sync , share _ clk , wp , comp n a , v osns 0 C , v orb 0 C ........................ C0.3 v to 3.6 v sgnd ........................................................ C0.3 v to 0.3 v temperatures internal operating temperature range ( notes 2, 3) ............................................ C40 c to 125 c storage temperature range .................. C55 c to 125 c peak package body temperature during reflow .. 245 c (note 1) v out0 1 2 3 4 5 6 7 top view 8 9 m l k j h g f e d c b a v in0 sgnd gnd v out1 v in1 bga package 108-lead (16mm 11.9mm 3.51mm) t jmax = 125c, jctop = 5.9c/w, jcbottom = 2.1c/w, jb = 2.7c/w, ja = 16c/w values determined per jesd51-12 weight = 1.7 grams order information part number pad or ball finish part marking* package type msl rating temperature range (see note 2) device finish code ltm4675ey#pbf sac305 (rohs) ltm4675y e1 bga 4 C40c to 125c ltm4675iy#pbf sac305 (rohs) ltm4675y e1 bga 4 C40c to 125c ltm4675iy snpb (63/37) ltm4675y e0 bga 4 C40c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and tray drawings: www.linear.com/packaging ltm 4675 4675f
4 for more information www.linear.com/ltm4675 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5v , frequency_ switch = 500khz and v outn commanded to 1.000v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units v in input dc voltage test circuit 1 test circuit 2; vin_off < vin_on = 4.25v l l 5.75 4.5 17 5.75 v v v outn range of output voltage regulation v out0 differentially sensed on v osns0 + /v osns0 C pin-pair; v out1 differentially sensed on v osns1 /sgnd pin-pair; commanded by serial bus or with resistors present at start-up on v outn cfg and/or v trimn cfg l l 0.5 0.5 5.5 5.5 v v v outn (dc) output voltage, total variation with line and load (note 5 v outn low range (mfr_pwm_mode n [1] = 1 b ), frequency_switch = 425khz ) digital servo engaged (mfr_pwm_mode n [6] = 1 b ) digital servo disengaged (mfr_pwm_mode n [6] = 0 b ) l 0.995 0.985 1.000 1.000 1.005 1.015 v v input specifications i inrush(vin) input inrush current at start-up test circuit 1, v outn =1v, v in = 12v; no load besides capacitors; ton_rise n = 3ms 400 ma i q(svin) input supply bias current forced continuous mode, mfr_pwm_mode n [0] = 1 b run n = 5v, run 1-n = 0v shutdown, run 0 = run 1 = 0v 40 20 ma ma i s(vinn,psm) input supply current in pulse-skipping mode operation pulse-skipping mode, mfr_pwm_mode n [0] = 0 b , i outn = 100ma 20 ma i s(vinn,fcm) input supply current in forced -continuous mode operation forced continuous mode, mfr_pwm_mode n [0] = 1 b i outn = 100ma i outn = 9a 40 927 ma ma i s(vinn,shutdown) input supply current in shutdown shutdown, run n = 0v 50 a output specifications i outn output continuous current range (note 6) 0 9 a ?v outn(line) v outn line regulation accuracy digital servo engaged (mfr_pwm_mode n [6] = 1 b ) digital servo disengaged (mfr_pwm_mode n [6] = 0 b ) sv in and v inn electrically shorted together and intv cc open circuit; i outn = 0a, 5.75v v in 17v, v out low range (mfr_pwm_mode n [1] = 1 b ) frequency_switch = 425khz (referenced to 12v in ) (note 5) l 0.03 0.03 0.2 % %/v ?v outn(load) v outn load regulation accuracy digital servo engaged (mfr_pwm_mode n [6] = 1 b ) digital servo disengaged (mfr_pwm_mode n [6] = 0 b ) 0a i outn 9a, v out low range, (mfr_pwm_mode n [1] = 1 b ) frequency_switch = 425khz (note 5) l 0.03 0.2 0.5 % % v outn(ac) output voltage ripple 10 mv p-p f s (each channel) v outn ripple frequency frequency_switch set to 500khz (0xfbe8) l 462.5 500 537.5 khz ?v outn( start) turn -on overshoot ton_rise n = 3ms (note 12) 8 mv t start turn -on start-up time time from v in toggling from 0v to 12v to rising edge of gpio n . ton_delay n = 0ms, ton_rise n = 3ms, mfr_gpio_ propagate n = 0x0100, mfr_gpio_response n = 0x0000 l 60 70 ms ltm 4675 4675f
5 for more information www.linear.com/ltm4675 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5v , frequency_ switch = 500khz and v outn commanded to 1.000v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units t delay (0ms) turn -on delay time time from first rising edge of run n to rising edge of gpio n . ton_delay n = 0ms, ton_rise n = 3ms, mfr_gpio_ propagate n = 0x0100, mfr_gpio_response n = 0x0000. v in having been established for at least 70ms l 2.75 3.1 3.5 ms ?v outn (ls) peak output voltage deviation for dynamic load step load: 0a to 4.5a and 4.5a to 0a at 4.5a/s, figure 60 circuit, v outn = 1v, v in = 12v (note 12) 50 mv t settle settling time for dynamic load step load: 0a to 4.5a and 4.5a to 0a at 4.5a/s, figure 60 circuit, v outn = 1v, v in = 12v (note 12) 35 s i outn(ocl_pk) output current limit, peak cycle-by-cycle inductor peak current limit inception 15.8 a i outn(ocl_ avg ) output current limit, time averaged time-averaged output inductor current limit inception threshold, commanded by iout_oc_fault_limit n (note 12) 10.8a; see i o-rb-acc specification (output current readback accuracy) control section v fbcm0 channel 0 feedback input common mode range v osns0 C valid input range (referred to sgnd) v osns0 + valid input range (referred to sgnd) l l C0.1 0.3 5.7 v v v fbcm1 channel 1 feedback input common mode range sgnd valid input range (referred to gnd) v osns1 valid input range (referred to sgnd) l l C0.3 0.3 5.7 v v v out-rng0 full-scale command voltage , range 0 (notes 7, 15) v outn commanded to 5.500v, mfr_pwm_mode n [1] = 0 b resolution lsb step size 5.422 12 1.375 5.576 v bits mv v out-rng1 full-scale command voltage , range 1 (notes 7, 15) v outn commanded to 2.750v, mfr_pwm_mode n [1] = 1 b resolution lsb step size 2.711 12 0.6875 2.788 v bits mv r vsense0 + v osns0 + impedance to sgnd 0.05v v vosns0 + C v sgnd 5.5v 41 k r vsense1 v osns1 impedance to sgnd 0.05v v vosns1 C v sgnd 5.5v 37 k t on(min) minimum on- time (note 8 ) 90 ns analog ov/ uv ( overvoltage/ undervoltage) output voltage supervisor comparators ( vout_ ov/ uv_ fault_ limit and vout_ ov/ uv_ warn_ limit monitors) n ov /uv_comp resolution, output voltage supervisors (note 15) 8 bits v ov-rng output ov comparator threshold detection range (note 15) high range scale, mfr_pwm_mode n [1] = 0 b low range scale, mfr_pwm_mode n [1] = 1 b 1 0.5 5.6 2.7 v v v ou-stp output ov and uv comparator threshold programming lsb step size (note 15) high range scale, mfr_pwm_mode n [1] = 0 b low range scale, mfr_pwm_mode n [1] = 1 b 22 11 mv mv ltm 4675 4675f
6 for more information www.linear.com/ltm4675 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5v , frequency_ switch = 500khz and v outn commanded to 1.000v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units v ov-acc output ov comparator threshold accuracy (see note 14) 2 v v vosns0 + C v vosns0 C 5.6v, mfr_pwm_mode 0 [1] = 0 b 1 v v vosns0 + C v vosns0 C 2.7v, mfr_pwm_mode 0 [1] = 1 b 0.5 v v vosns0 + C v vosns0 C < 1v, mfr_pwm_mode 0 [1] = 1 b 2 v v vsense1 C v sgnd 5.6v, mfr_pwm_mode 1 [1] = 0 b 1.5 v v vsense1 C v sgnd 2.7v, mfr_pwm_mode 1 [1] = 1 b 0.5 v v vsense1 C v sgnd < 1.5v, mfr_pwm_mode 1 [1] = 1 b l l l l l l 2 2 20 2 2 30 % % mv % % mv v uv-rng output uv comparator threshold detection range (note 15) high range scale, mfr_pwm_mode n [1] = 0 b low range scale, mfr_pwm_mode n [1] = 1 b 1 0.5 5.4 2.7 v v v uv-acc output uv comparator threshold accuracy (see note 14) 2 v v vsense0 + C v vsense0 C 5.4v, mfr_pwm_mode 0 [1] = 0 b 1 v v vsense0 + C v vsense0 C 2.7v, mfr_pwm_mode 0 [1] = 1 b 0.5 v v vsense0 + C v vsense0 C < 1v, mfr_pwm_mode 0 [1] = 1 b 2 v v vosns1 C v sgnd 5.4v, mfr_pwm_mode 1 [1] = 0 b 1.5 v v vosns1 C v sgnd 2.7v, mfr_pwm_mode 1 [1] = 1 b 0.5 v v vosns1 C v sgnd < 1.5v, mfr_pwm_mode 1 [1] = 1 b l l l l l l 2 2 20 2 2 30 % % mv % % mv t prop-ov output ov comparator response times overdrive to 10% above programmed threshold 35 s t prop-uv output uv comparator response times underdrive to 10% below programmed threshold 50 s analog ov/uv sv in input voltage supervisor comparators (threshold detectors for vin_on and vin_off) n svin-ov/uv-comp sv in ov/uv comparator threshold-programming resolution (note 15) 8 bits sv in-ou-range sv in ov/uv comparator threshold-programming range l 4.5 20 v sv in-ou-stp sv in ov/uv comparator threshold-programming lsb step size (note 15) 82 mv sv in-ou-acc sv in ov/uv comparator threshold accuracy 9v < sv in 20v 4.5v sv in 9v l l 2.5 225 % mv t prop- svin- high- vin sv in ov/uv comparator response time, high v in operating configuration test circuit 1, and: vin_on = 9v; sv in driven from 8.775v to 9.225v vin_off = 9v; sv in driven from 9.225v to 8.775v l l 35 35 s s t prop-svin-low-vin sv in ov/uv comparator response time, low v in operating configuration test circuit 2, and: vin_on = 4.5v; sv in driven from 4.225v to 4.725v vin_off = 4.5v; sv in driven from 4.725v to 4.225v l l 35 35 s s channels 0 and 1 output voltage readback (read_vout n ) n vo-rb output voltage readback resolution and lsb step size (note 15) 16 244 bits v v o-f/s output voltage full-scale digitizable range v runn = 0v (notes 7, 15) 8 v v o-rb-acc output voltage readback accuracy channel 0: 1v v vosns0 + C v vosns0 C 5.5v channel 0: 0.6 v v vosns0 + C v vosns0 C < 1v channel 1: 1v v vosns1 C v sgnd 5.5v channel 1: 0.6v v vosns1 C v sgnd < 1v l l l l within 0.5% of reading within 5mv of reading within 0.5% of reading within 5mv of reading ltm 4675 4675f
7 for more information www.linear.com/ltm4675 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5v , frequency_ switch = 500khz and v outn commanded to 1.000v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units t convert -vo-rb output voltage readback update rate mfr_adc_control=0x00 (notes 9, 15) mfr_adc_control=0x0d (notes 9, 15) mfr_adc_control=0x05 or 0x09 (notes 9, 15) 100 27 8 ms ms ms input voltage (sv in ) readback (read_vin) n svin-rb input voltage readback resolution and lsb step size (notes 10, 15) 10 15.625 bits mv sv in-f/s input voltage full-scale digitizable range (notes 11, 15) 38.91 v sv in-rb-acc input voltage readback accuracy read_vin, 4.5v sv in 17v l within 2% of reading t convert -svin-rb input voltage readback update rate mfr_adc_control=0x00 (notes 9, 15) mfr_adc_control=0x01 (notes 9, 15) 100 8 ms ms channels 0 and 1 output current ( read_ iout n ), duty cycle ( read_ duty_ cycle n ), and computed input current ( mfr_ read_ iin n ) readback n io-rb output current readback resolution and lsb step size (notes 10, 12) 10 15.6 bits ma i o-f/s , i i-f/s output current full-scale digitizable range and input current range of calculation (note 12) 40 a i o-rb-acc output current, readback accuracy read_iout n , channels 0 and 1, 0 i outn 9a, forced-continuous mode, mfr_pwm_mode n [1:0] = 10 b l within 225ma of reading i o-rb(9a) full load output current readback i outn = 9a (note 12). see histograms in typical performance characteristics 9 a n ii-rb computed input current, readback resolution and lsb step size (notes 10, 12) 10 1.95 bits ma i i-rb-acc computed input current, readback accuracy, neglecting i svin mfr_read_iin n , channels 0 and 1, 0 i outn 9a, forced-continuous mode, mfr_pwm_mode n [1:0] = 10 b , mfr_iin_offset n = 0ma l within 140ma of reading t convert -io-rb output current readback update rate mfr_adc_control=0x00 (notes 9, 15) mfr_adc_control=0x0d (notes 9, 15) mfr_adc_control=0x06 or 0x0a (notes 9, 15) 100 27 8 ms ms ms t convert -ii-rb computed input current, readback update rate mfr_adc_control=0x00 (notes 9, 15) 100 ms n duty -rb resolution, duty cycle readback (notes 10, 15) 10 bits d rb-acc duty cycle tue read_duty_cycle n , 16.3% duty cycle (note 15) 3 % t convert - duty-rb duty cycle readback update rate mfr_adc_control=0x00 (notes 9, 15) 100 ms temperature readback for channel 0, channel 1, and controller (respectively: read_temperature_1 0 , read_temperature_1 1 , and read_temperature_2) t res-rb temperature readback resolution channel 0, channel 1, and controller (note 15) 0.0625 c t rb-ch-acc(72mv) channel temperature tue, switching action off channels 0 and 1, pwm inactive, run n = 0v, ?v tsnsna = 72mv l within 3c of reading ltm 4675 4675f
8 for more information www.linear.com/ltm4675 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5v , frequency_ switch = 500khz and v outn commanded to 1.000v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units t rb-ch-acc(on) channel temperature tue, switching action on read_temperature_1 n , channels 0 and 1, pwm active, run n = 5v (note 12) within 3c of reading t rb-ctrl-acc(on) control ic die temperature tue, switching action on read_temperature_2, pwm active, run 0 = run 1 = 5v (note 12) within 1c of reading t convert -temp-rb temperature readback update rate mfr_adc_control=0x00 (notes 9, 15) mfr_adc_control=0x06 or 0x0a (notes 9, 15) 100 8 ms ms intv cc regulator v intvcc internal v cc voltage no load 6v v in 17v 4.8 5 5.2 v ?v intvcc (load) v intvcc intv cc load regulation 0ma i intvcc 50ma 0.5 2 % v dd33 regulator v vdd33 internal v dd33 voltage 3.2 3.3 3.4 v i lim(vdd33) v dd33 current limit v dd33 electrically short- circuited to gnd 70 ma v vdd33_ov v dd33 overvoltage threshold (note 15) 3.5 v v vdd33_uv v dd33 undervoltage threshold (note 15) 3.1 v v dd25 regulator v vdd25 internal v dd25 voltage 2.5 v i lim(vdd25) v dd25 current limit v dd 25 electrically short- circuited to gnd 50 ma oscillator and phase-locked loop (pll) f osc oscillator frequency accuracy frequency_switch = 500khz (0xfbe8) 250khz frequency_switch 1mhz (note 15) l 7.5 7.5 % % f sync pll sync capture range (note 16) l 225 1100 khz v th,sync sync input threshold v sync rising (note 15) v sync falling (note 15) 1.5 1 v v v ol,sync sync low output voltage i sync = 3ma l 0.3 0.4 v i sync sync leakage current in frequency slave mode 0v v sync 3.6v mfr_config_all[4]=1 b l 5 a sync -0 sync-to-channel 0 phase relationship, lag from falling edge of sync to rising edge of top mosfet (mt0) gate (note 15) mfr_pwm_config[2:0] = 000 b , 01x b mfr_pwm_config[2:0] = 101 b mfr_pwm_config[2:0] = 001 b mfr_pwm_config[2:0] = 1x0 b 0 60 90 120 deg deg deg deg sync -1 sync-to-channel 1 phase relationship, lag from falling edge of sync to rising edge of top mosfet (mt1) gate (note 15) mfr_pwm_config[2:0] = 011 b mfr_pwm_config[2:0] = 000 b mfr_pwm_config[2:0] = 010 b , 10x b mfr_pwm_config[2:0] = 001 b mfr_pwm_config[2:0] = 110 b 120 180 240 270 300 deg deg deg deg deg ltm 4675 4675f
9 for more information www.linear.com/ltm4675 electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2). specified as each individual output channel ( note 4). t a = 25c , v in = 12v , run n = 5v , frequency_ switch = 500khz and v outn commanded to 1.000v unless otherwise noted. configured with factory- default eeprom settings and per test circuit 1, unless otherwise noted. symbol parameter conditions min typ max units eeprom characteristics endurance (note 13) 0c t j 85c during eeprom write operations (note 3) l 10,000 cycles retention (note 13) t j < t j(max) , with most recent eeprom write operation having occurred at 0c t j 85c (note 3) l 10 years mass_write mass write operation time execution of store_user_all command, 0c t j 85c ( ate - tested at t j = 25c) (notes 3, 13) 440 4100 ms digital i/os v ih input high threshold voltage scl, sda, run n , gpio n (note 15) share_clk, wp (note 15) 2.0 1.8 v v v il input low threshold voltage scl, sda, run n , gpio n (note 15) share_clk, wp (note 15) 1.4 0.6 v v v hyst input hysteresis scl, sda (note 15) 80 mv v ol output low voltage scl, sda, alert, run n , gpio n , share_clk: i sink = 3ma l 0.3 0.4 v i ol input leakage current sda, scl, alert, run n : 0v v pin 5.5v gpio n and share_clk: 0v v pin 3.6v l l 5 2 a a t filter input digital filtering run n (note 15) gpio n (note 15) 10 3 s s c pin input capacitance scl, sda, run n , gpio n , share_clk, wp (note 15) 10 pf pmbus interface timing characteristics f smb serial bus operating frequency (note 15) 10 400 khz t buf bus free time between stop and start (note 15) 1.3 s t hd, sta hold time after repeated start condition time period after which first clock is generated (note 15) 0.6 s t su, sta repeated start condition setup time (note 15) 0.6 s t su,sto stop condition setup time (note 15) 0.6 s t hd, dat data hold time receiving data (note 15) transmitting data (note 15) 0 0.3 0.9 s s t su, dat data setup time receiving data (note 15) 0.1 s t timeout_smb stuck pmbus timer timeout measured from the last pmbus start event: block reads, mfr_config_all[3]=0 b (note 15) non-block reads, mfr_config_all[3]=0 b (note 15) mfr_config_all[3]=1 b (note 15) 150 32 250 ms ms ms t low serial clock low period (note 15) 1.3 10000 s t high serial clock high period (note 15) 0.6 s ltm 4675 4675f
10 for more information www.linear.com/ltm4675 electrical characteristics note 1: stresses beyond those listing under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. note 2: the ltm4675 is tested under pulsed-load conditions such that t j t a . the ltm4675e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4675i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: the ltm4675s eeprom temperature range for valid write commands is 0c to 85c. to achieve guaranteed eeprom data retention, execution of the store_user_all commandi.e., uploading ram contents to nvmoutside this temperature range is not recommended. however, as long as the ltm4675s eeprom temperature is less than 130c, the ltm4675 will obey the store_ user_all command. only when eeprom temperature exceeds 130c, the ltm4675 will not act on any store_user_all transactions: instead, the ltm4675 nacks the serial command and asserts its relevant cml (communications, memory, logic) fault bits. eeprom temperature can be queried prior to commanding store_user_all; see the applications information section. note 4: the two power inputsv in0 and v in1 and their respective power outputsv out0 and v out1 are tested independently in production. a shorthand notation is used in this document that allows these parameters to be refered to by v inn and v outn , where n is permitted to take on a value of 0 or 1. this italicized, subscripted n notation and convention is extended to encompass all such pin names, as well as register names with channel-specific, i.e., paged data. for example, vout_command n refers to the vout_command command code data located in pages 0 and?1, which in turn relate to channels 0 (v out0 ) and channel 1 (v out1 ). registers containing non-page-specific data, i.e., whose data is global to the module or applies to both of the module's channels lack the italicized, subscripted n , e.g., frequency_switch. note 5: v outn (dc) and line and load regulation tests are performed in production with digital servo disengaged (mfr_pwm_mode n [6]?=?0 b ) and low v outn range selected (mfr_pwm_mode n [1]) = 1 b . the digital servo control loop is exercised in production (setting mfr_pwm_ mode n [6] = 1 b ), but convergence of the output voltage to its final settling value is not necessarily observed in final testdue to potentially long time constants involvedand is instead guaranteed by the output voltage readback accuracy specification. evaluation in application demonstrates capability; see the typical performance characteristics section. note 6: see output current derating curves for different v in , v out , and t a , located in the applications information section. note 7: even though v out0 and v out1 are specified for 6v absolute maximum, the maximum recommended regulation-command voltage is: 5.5v for a high-v out range setting of mfr_pwm_mode n [1]=0 b ; 2.5v for a low-v out range setting of mfr_pwm_mode n [1]=1 b . note 8: minimum on-time is tested at wafer sort. note 9: data conversion is performed in round-robin (cyclic) fashion. all telemetry signals are continuously digitized, and reported data is based on measurements not older than 100ms, typical. some telemetry parameters can be digitized at a faster update rate by configuring mfr_ adc_control. note 10: the following telemetry parameters are formatted in pmbus- defined linear data format, in which each register contains a word comprised of 5 most significant bitsrepresenting a signed exponent, to be raised to the power of 2and 11 least significant bitsrepresenting a signed mantissa: input voltage (on sv in ), accessed via the read_vin command code; output currents (i outn ), accessed via the read_iout n command codes; module input current (i vin0 + i vin1 + i svin ), accessed via the read_iin command code; channel input currents (i vinn + 1/2 ? i svin ), accessed via the mfr_read_iin n command codes;and duty cycles of channel 0 and channel 1 switching power stages, accessed via the read_ duty_cycle n command codes. this data format limits the resolution of telemetry readback data to 10 bits even though the internal adc is 16 bits and the ltm4675s internal calculations use 32-bit words. note 11: the absolute maximum rating for the sv in pin is 20v. input voltage telemetry (read_vin) is obtained by digitizing a voltage scaled down from the sv in pin. note 12: these typical parameters are based on bench measurements and are not production tested. note 13: eeprom endurance and retention are guaranteed by wafer-level testing for data retention. the minimum retention specification applies for devices whose eeprom has been cycled less than the minimum endurance specification, and whose eeprom data was written to at 0c t j 85c. downloading nvm contents to ram by executing the restore_user_all or mfr _reset commands is valid over the entire operating temperature range and does not influence eeprom characteristics. note 14: channel 0 ov/uv comparator threshold accuracy for mfr_pwm_mode 0 [1] = 1 b tested in ate at v vosns0 + C v vosns0 C = 0.5v and 2.7v. 1v condition tested at ic-level, only. channel 1 ov/uv comparator threshold accuracy for mfr_pwm_mode 1 [1] = 1 b tested in ate with v vosns 1 -v sgnd = 0.5v and 2.7v. 1.5v condition tested at ic-level, only. note 15: tested at ic-level ate . note 16: pll sync capture range tested with frequency_switch set to frequency slave mode (0x0000), with mfr_config_all[4] = 1 b , and with sync driven by external clock. low end of sync capture range (225khz) verified at v in = 5.75v and v outn = 2.5v. high end of sync capture range (1.1mhz) verified at v in = 12v and v outn = 3.3v. ltm 4675 4675f
11 for more information www.linear.com/ltm4675 typical performance characteristics efficiency vs load current at 5v in efficiency vs load current at 8v in efficiency vs load current at 12v in t a = 25c, 12v in to 1v out , unless otherwise noted. output current (a) 0 2 4 80 90 18 70 65 6 8 10 12 14 16 100 75 85 95 efficiency (%) 4675 g01 3.3v out , 650khz 2.5v out , 650khz 1.8v out , 650khz 1.5v out , 575khz 1.2v out , 500khz 1.0v out , 500khz 0.9v out , 425khz output current (a) 0 2 4 80 90 18 70 65 6 8 10 12 14 16 100 75 85 95 efficiency (%) 4675 g02 5.0v out , 1mhz 3.3v out , 1mhz 2.5v out , 1mhz 1.8v out , 750khz 1.5v out , 650khz 1.2v out , 575khz 1.0v out , 500khz 0.9v out , 525khz single phase single output pulse-skipping (discontinuous) mode efficiency, v in = sv in = v inn , intv cc open, mfr_pwm_mode n [0] = 0 b output current (a) 0 1 2 50 70 9 4675 g04 40 3 4 5 6 7 8 90 60 80 12v in to 1.5v out , 650khz efficiency (%) dual phase single output?load transient response,12v in to 1v out single phase single output?load transient response,12v in to 1v out dual phase single output?load transient response, 5v in to 1v out v out 20mv/div ac-coupled i out 10a/div 50s/div figure 27 circuit at 12v in , intv cc pin open circuit and vout_command n set to 1.000v. 8a to 18a load step at 10a/s 4675 g05 v out0 50mv/div ac-coupled i out 5a/div 40s/div figure 60 circuit at 12v in 0a to 5a load step at 5a/s 4675 g06 v out 20mv/div ac-coupled i out 10a/div 50s/div figure 27 circuit at 5v in , vout_command n set to 1.000v. 8a to 18a load step at 10a/s 4675 g07 dual output concurrent rail start-up/shutdown dual output start-up/shutdown with a pre-biased load v out0 , v out1 500mv/div i out0 5a/div run 0 , run 1 5v/div 2ms/div figure 60 circuit at 12v in , 112m load on v out0 , no load on v out1 . ton_rise 0 = 3ms, ton_rise 1 = 5.297ms, toff_delay 1 = 0ms, toff_delay 0 = 2.43ms, toff_fall 1 = 5.328ms, toff_fall 0 = 3ms, on_off_config n = 0x1e 4675 g08 v out0 , v out1 500mv/div i diode 1ma/div run 0 , run 1 5v/div 2ms/div figure 60 circuit at 12v in , 112m load on v out0 , 500 on v out1 . v out1 pre-biased through a diode. ton_rise 0 = 3ms, ton_rise 1 = 5.297ms, toff_delay 1 = 0ms, toff_delay 0 = 2.43ms, toff_fall 1 = 5.328ms, toff_fall 0 = 3ms, on_off_config 1 = 0x1f on_off_config 0 = 0x1e 4675 g09 output current (a) 0 2 4 80 90 18 70 65 6 8 10 12 14 16 100 75 85 95 efficiency (%) 4675 g03 5.0v out , 1mhz 3.3v out , 1mhz 2.5v out , 1mhz 1.8v out , 750khz 1.5v out , 650khz 1.2v out , 575khz 1.0v out , 500khz 0.9v out , 525khz ltm 4675 4675f
12 for more information www.linear.com/ltm4675 read_temperature_2 (control ic temperature error) vs junction temperature, run n = 0v read_vin (input voltage readback telemetry) error vs sv in , run n = 0v mfr_read_iin n (input current readback) error vs (i vinn + i svin ), mfr_pwm_mode n [0]=1 b , i outn swept from 0a to 9a, one channel at a time, run 1-n = 0v single phase single output short- circuit protection at full load read_vout n (output voltage readback) error vs v outn i outn = no load, run 1-n = 0v read_iout n (output current readback) error vs i outn typical performance characteristics t a = 25c, 12v in to 1v out , unless otherwise noted. single phase single output? short-circuit protection at no load actual temperature (c) ?45 ?1.0 measurement error (c) ?0.8 ?0.4 ?0.2 0 1.0 0.4 ?5 35 55 4675 g14 ?0.6 0.6 0.8 0.2 ?25 15 75 95 115 v out0 200mv/div i in0 1a/div 10s/div figure 60 circuit at 12v in , no load on v out0 prior to application of short circuit 4675 g10 v out0 200mv/div i in0 1a/div 10s/div figure 60 circuit at 12v in , 112m load on v out0 prior to application of short circuit 4675 g11 v out (v) 0.5 measurement error (mv) 0 20 30 4.5 4675 g12 ?20 ?10 10 ?30 1.5 2.5 3.5 5.5 specified upper limit specified lower limit channel 0 channel 1 sv in (v) 4 ?400 measurement error (mv) ?200 0 200 400 8 12 16 20 specified upper limit specified lower limit 4675 g15 i inn + i svin (a) 0 ?160 measurement error (ma) ?120 ?80 ?40 0 120 80 40 160 0.2 0.4 0.6 0.8 4675 g16 1.0 channel 1 channel 0 specified upper limit specified lower limit i out (a) 0 ?300 measurement error (ma) ?200 ?100 0 100 channel 0 channel 1 200 300 3 6 9 specified upper limit specified lower limit 4675 g13 ltm 4675 4675f
13 for more information www.linear.com/ltm4675 pin functions package row and column labeling m ay vary among module products. review each package layout carefully. gnd (a2-8, b2-7, c2, c4-8, d2, d5, e1, e9, f1, f8, g1, g8-9, h1, h8-9, j2, j8, k2, k5-8, l2-7, m2-8): power ground of the ltm 4675 . power return for v out 0 and v out 1 . v out0 (a1, b1, c1, d1): channel 0 output voltage. v osns 0 + ( d 7): channel 0 positive differential voltage sense input . together , v osns 0 + and v osns 0 C serve to kelvin - sense the v out 0 output voltage at v out0 s point of load (pol) and provide the differential feedback signal directly to channel 0s control loop and voltage supervisor circuits . v out0 can regulate up to 5.5v output. command v out0 s target regulation voltage by serial bus. its initial command value at sv in power-up is dictated by nvm (non-volatile memory ) contents ( factory default: 1.000v)or, option- ally, may be set by configuration resistors; see v out0cfg , v trim0cfg and the applications information section. v osns0 C (e7): channel 0 negative differential voltage sense input. see v osns0 + . typical performance characteristics t a = 25c, 12v in to 1v out , unless otherwise noted. read_iout of 26 ltm4675s (dc2053) 12v in , 1v out , t j = C40c, i outn = 9a, system having reached thermally steady-state condition, no airflow read_iout of 26 ltm4675s (dc2053) 12v in , 1v out , t j = 25c, i outn = 9a, system having reached thermally steady-state condition, no airflow read_iout of 26 ltm4675s (dc2053) 12v in , 1v out , t j = 125c, i outn = 9a, system having reached thermally steady-state condition, no airflow read_iout channel readback (a) number of channels 4675 g17 0 2 4 6 8 10 12 14 9.00000 9.03125 9.06250 9.09375 9.12500 9.15625 9.18750 9.21875 9.25000 read_iout channel readback (a) number of channels 4675 g18 0 2 4 6 8 10 12 14 8.87500 8.90625 8.93750 8.96875 9.00000 9.03125 9.06250 9.09375 9.12500 read_iout channel readback (a) number of channels 4675 g19 0 2 4 6 8 10 12 14 8.81250 8.84375 8.87500 8.90625 8.93750 8.96875 9.00000 9.03125 9.06250 v orb0 + (d8): channel 0 positive readback pin. shorted to v osns0 + internal to the ltm4675. if desired, place a test point on this node and measure its impedance to v out0 on ones hardware (e.g., motherboard, during in circuit test (ict) post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between v osns0 + and v out0 . v orb0 C (e8): channel 0 negative readback pin. shorted to v osns0 C internal to the ltm4675. if desired, place a test point on this node and measure its impedance to gnd on ones hardware (e.g., motherboard, during ict post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between v osns0 C and gnd (v out0 power return). v out1 (j1, k1, l1, m1): channel 1 output voltage. v osns1 ( h7): channel 1 positive voltage sense input. connect v osns1 to v out1 at the pol. this provides the feedback signal for channel 1s control loop and voltage supervisor circuits . v out1 can regulate up to 5.5v output. command v out1 s target regulation voltage by serial bus. its initial command value at sv in power-up is dictated by ltm 4675 4675f
14 for more information www.linear.com/ltm4675 pin functions nvm (non-volatile memory ) contents ( factory default: 1.000v)or, optionally, may be set by configuration resistors; see v out1cfg , v trim1cfg and the applications information section. sgnd ( f 5-6, g 5-6): channel 1 negative voltage sense input . see v osns1 . additionally, sgnd is the signal ground return path of the ltm4675. if desired, one may place a test point on one of the four sgnd pins and measure its impedance to gnd on one s hardware ( e . g ., motherboard, during ict post- assembly process) to provide a means of verifying the integrity of the feedback signal connection between the other three sgnd pins and gnd ( v out1 power return ). sgnd is not electrically connected to gnd internal to the ltm4675. connect sgnd to gnd local to the ltm4675. v orb1 (j7): channel 1 positive readback pin. shorted to v osns1 internal to the ltm4675. at ones option, place a test point on this node and measure its impedance to v out1 on ones hardware (e.g., motherboard, during ict post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between v out1 and v osns1 . v in0 (a9, b9, c9, d9): positive power input to channel 0 switching stage . provide sufficient decoupling capacitance in the form of multilayer ceramic capacitors (mlccs) and low esr electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. mlccs should be placed as close to the ltm4675 as physically possible. see layout recommendations in the applications information section. v in1 (j9, k9, l9, m9): positive power input to channel 1 switching stage. provide sufficient decoupling capaci- tance in the form of mlccs and low esr electrolytic (or equivalent ) to handle reflected input current ripple from the step-down switching stage. mlccs should be placed as close to the ltm4675 as physically possible. see layout recommendations in the applications information section . sw 0 (b8): switching node of channel 0 step-down con- verter stage. used for test purposes or emi- snubbing. may be routed a short distance to a local test point to monitor switching action of channel 0, if desired, but do not route near any sensitive signals; otherwise , leave electrically isolated (open). sw 1 (l8): switching node of channel 1 step-down con- verter stage. used for test purposes or emi- snubbing. may be routed a short distance to a local test point to monitor switching action of channel 1, if desired, but do not route near any sensitive signals; otherwise, leave open. sv in (f9): input supply for ltm4675s internal control ic. in most applications, sv in connects to v in0 and/or v in1 , in which case no external decoupling beyond that already allocated for v in0 /v in1 is required. if sv in is operated from an auxiliary supply separate from v in0 /v in1 , decouple this pin to gnd with a capacitor (0.1f to 1f). intv cc (f7, g7): internal regulator, 5v output. when operating the ltm4675 from 5.75v sv in 17 v, an ldo generates intv cc from sv in to bias internal control circuits and the mosfet drivers of the ltm4675. no external decoupling is required. intv cc is regulated regardless of the run n pin state. when operating the ltm4675 with 4.5v sv in < 5.75v, intv cc must be electrically shorted to sv in . v dd33 ( j 5): internally generated 3.3v power supply output pin. this pin should only be used to provide ex- ternal current for the pull-up resistors required for gpio n , share_clk, and sync, and may be used to provide external current for pull-up resistors on run n , sda, scl and alert. no external decoupling is required. v dd 25 ( j 4): internally generated 2.5 v power supply output pin. do not load this pin with external current; it is used strictly to bias internal logic and provides current for the internal pull-up resistors connected to the configuration- programming pins. no external decoupling is required. asel (g2): serial bus address configuration pin. on any given i 2 c/smbus serial bus segment, every device must have its own unique slave address. if this pin is left open, the ltm4675 powers up to its default slave address of 0x4f (hexadecimal), i.e., 1001111 b ( industry standard convention is used throughout this document : 7- bit slave addressing). the lower four bits of the ltm4675s slave address can be altered from this default value by connecting a resistor from this pin to sgnd. minimize capacitanceespecially when the pin is left opento assure accurate detection of the pin state. ltm 4675 4675f
15 for more information www.linear.com/ltm4675 pin functions f swphcfg (h2): switching frequency, channel phase- interleaving angle and phase relationship to sync configuration pin . if this pin is left open or , if the ltm 4675 is configured to ignore pin-strap (rconfig) resistors, i.e., mfr_config_all[6] = 1 b then the ltm4675s switching frequency ( frequency _ switch ) and channel phase relationships (with respect to the sync clock; mfr_pwm_config[2:0]) are dictated at sv in power- up according to the ltm4675s nvm contents. default factory values are: 500khz operation; channel 0 at 0; and channel 1 at 180 c ( convention throughout this document : a phase angle of 0 means the channels switch node rises coincident with the falling edge of the sync pulse). connecting a resistor from this pin to sgnd (and using the factory - default nvm setting of mfr_ config _ all[6] = 0 b ) allows a convenient way to configure multiple ltm4675s with identical nvm contents for different switching frequen - cies of operation and phase interleaving angle settings of intra- and extra-module-paralleled channelsall, without gui intervention or the need to custom pre-program module nvm contents. (see the applications information section.) minimize capacitanceespecially when the pin is left opento assure accurate detection of the pin state. v out0cfg (g3): output voltage select pin for v out0 , coarse setting. if the v out0cfg and v trim0cfg pins are both left openor, if the ltm4675 is configured to ignore pin- strap ( rconfig ) resistors , i . e ., mfr_ config _ all [6] = 1 b then the ltm4675s target v out0 output voltage setting ( vout _ command 0 ) and associated power - good and ov/ uv warning and fault thresholds are dictated at sv in power-up according to the ltm4675s nvm contents. a resistor connected from this pin to sgnd in combination with resistor pin settings on v trim0cfg , and using the factory-default nvm setting of mfr_config_all[6] = 0 b can be used to config- ure the ltm4675s channel 0 output to power-up to a vout_command value ( and associated output voltage monitoring and protection / fault - detection thresholds ) different from those of nvm contents . ( see the applications information section .) connecting resistor ( s ) from v out0 cfg to sgnd and / or v trim 0 cfg to sgnd in this manner allows a convenient way to configure multiple ltm4675s with identical nvm contents for different output voltage settingsall without gui intervention or the need to custom-pre -program module nvm contents. minimize capacitanceespecially when the pin is left opento assure accurate detection of the pin state. note that use of rconfigs on v out0cfg /v trim0cfg can affect the v out0 range setting (mfr_pwm_mode 0 [1]) and loop gain. v trim0cfg (h3): output voltage select pin for v out0 , fine setting. works in combination with v out0cfg to affect the vout_command (and associated output voltage monitoring and protection / fault - detection thresholds ) of channel ?0, at sv in power-up. (see v out0cfg and the applications information section .) minimize capacitance especially when the pin is left opento assure accurate detection of the pin state. note that use of rconfigs on v out0cfg /v trim0cfg can affect the v out0 range setting (mfr_pwm_mode 0 [1]) and loop gain. v out1cfg (g4): output voltage select pin for v out1 , coarse setting. if the v out1cfg and v trim1cfg pins are both left openor, if the ltm4675 is configured to ignore pin- strap ( rconfig ) resistors , i . e ., mfr_ config _ all [6] = 1 b then the ltm4675s target v out1 output voltage setting ( vout _ command 1 ) and associated ov / uv warning and fault thresholds are dictated at sv in power - up according to the ltm4675s nvm contents, in precisely the same fashion that the v out0cfg and v trim0cfg pins affect the respective settings of v out0 / channel 0. ( see v out0cfg , v trim0cfg and the applications information section.) minimize capacitanceespecially when the pin is left opento assure accurate detection of the pin state. note that use of rconfigs on v out1cfg /v trim1cfg can affect the v out1 range setting (mfr_pwm_mode 1 [1]) and loop gain. v trim1cfg (h4): output voltage select pin for v out1 , fine setting. works in combination with v out1cfg to affect the vout_command (and associated output voltage monitoring and protection / fault - detection thresholds ) of channel ?1, at sv in power-up. (see v out 1cfg and the applications information section .) minimize capacitance especially when the pin is left opento assure accurate detection of the pin state. note that use of rconfigs on v out1cfg /v trim1cfg can affect the v out1 range setting (mfr_pwm_mode 1 [1]) and loop gain. ltm 4675 4675f
16 for more information www.linear.com/ltm4675 pin functions sync (e5): pwm clock synchronization input and open- drain output pin . the setting of the frequency _switch command dictates whether the ltm 4675 is a sync master or sync slave module. when the ltm4675 is a sync master, frequency_switch contains the commanded switching frequency of channels 0 and 1in pmbus linear data formatand it drives its sync pin low for 500ns at a time, at this commanded rate. in contrast, a sync slave uses mfr_config_all[4]=1 b and does not pull its sync pin low. the ltm4675s pll synchronizes the ltm4675s pwm clock to the waveform present on the sync pinand therefore, a resistor pull-up to 3.3v is required in the application, regardless of whether the ltm4675 is a sync master or slave. exception : driving the sync pin with an external clock is permissible; see the applications information section for details. scl (e4): serial bus clock open-drain input (can be an input and output, if clock stretching is enabled). a pull-up resistor to 3.3v is required in the application for digital communication to the smbus master(s) that nominally drive this clock . the ltm 4675 will never encounter scenarios where it would need to engage clock stretching unless scl communication speeds exceed 100khzand even then, ltm4675 will not clock stretch unless clock stretching is enabled by means of setting mfr_ config_ all[1] = 1 b . the factory- default nvm configuration setting has mfr _config _all [1] = 0 b : clock stretching disabled. if communication on the bus at clock speeds above 100khz is required, the users smbus master(s) need to implement clock stretching support to assure solid serial bus communications, and only then should mfr_config_all[1] be set to 1 b . when clock stretching is enabled, scl becomes a bidirectional, open- drain output pin on ltm4675. sda (d4): serial bus data open-drain input and output. a pull-up resistor to 3.3v is required in the application. alert (e3): open-drain digital output. a pull-up resistor to 3.3v is required in the application only if smbalert interrupt detection is implemented in one s smbus system . share _ clk ( h 5): share clock , bidirectional open - drain clock sharing pin. nominally 100khz. used for synchronizing the time base between multiple ltm4675s (and any other linear technology devices with a share_ clk pin)to realize well-defined rail sequencing and rail tracking. tie the share_clk pins of all such devices together; all devices with a share_ clk pin will synchronize to the fastest clock. a pull-up resistor to 3.3v is required when synchronizing the time base between multiple devices. if synchronizing the time base between multiple devices is not needed and mfr_chan_config n [2]?=?0 b , only then is a pull-up resistor not required. g p i o 0 , g p i o 1 ( e 2 and f 2, respectively ): digital , programmable general purpose inputs and outputs . open-drain outputs and/or high impedance inputs. the ltm4675 s factory- default nvm configurations for mfr _ gpio _ propagate n 0 x 6893 and mfr _ gpio _ response n 0xc0are such that: (1) when a channel- specific fault condition is detectedsuch as channel ot ( overtemperature ) or output uv / ov the respective gpio n pin pulls logic low; (2) when a non-channel specific fault condition is detectedsuch as input ov or control ic otboth gpio n pins pull logic low; (3) the ltm4675 ceases switching action on channel 0 and 1 when its respective gpio n pin is logic low. most significantly, this default configuration provides for graceful integration and inter-operation of ltm4675 with paralleled channel(s) of other ltm4675(s )in terms of properly coordinating efforts in starting , ceasing , and resuming switching action and output voltage regulation, in unison all without gui intervention or the need to custom - preprogram module nvm contents. pull-up resistors from gpio n to 3.3v are required for proper operation in the vast majority of applications. (only if the ltm4675s mfr_gpio_response n value were set to 0x00 might pull -ups be unnecessary . see the applications information section for details.) ltm 4675 4675f
17 for more information www.linear.com/ltm4675 pin functions wp (k4): write protect pin, active high. an internal 10a current source pulls this pin to v dd33 . if wp is open circuit or logic high, only i 2 c writes to page, operation, clear_faults, mfr_clear_peaks and mfr_ee_unlock are supported. additionally, individual faults can be cleared by writing 1 b s to bits of interest in registers prefixed with status. if wp is low, i 2 c writes are unrestricted. run 0 , run 1 (f3 and f4, respectively): enable run input for channels 0 and 1, respectively. open-drain input and output. logic high on these pins enables the respective outputs of the ltm4675. these open-drain output pins hold the pin low until the ltm4675 is out of reset and sv in is detected to exceed vin_on. a pull -up resistor to 3.3v is required in the application. do not pull run logic high with a low impedance source. tsns 0 (c3 and d3): temperature sensor node for chan- nel ?0. pads c3 and d3 are connected to each other inter - nal to the module. it is permissible to leave these pads electrically open circuit and to only solder these pins to mounting pads on the pc board for mechanical integrity purposes. however, it is acceptable to electrically connect c3 to d3 on the pc board. tsns 1a , tsns 1b (j3 and k3, respectively): channel 1 temperature excitation/ measurement and thermal sensor pins, respectively. in most applications, connect tsns 1a to tsns 1b . this allows the ltm4675 to monitor the power stage temperature of channel 1. see the applications information section for information on how to use tsns 1a to monitor a temperature sensor external to the module, e.g., a pn junction on the die of a microprocessor. comp 0a , comp 1a (e6 and h6, respectively): current control threshold and error amplifier compensation nodes for channels 0 and 1, respectively. the trip threshold of each channels current comparator increases with a respective rise in comp n a voltage. small filter capacitors (22 pf) internal to the ltm4675 on these comp pins (ter - minated to sgnd) introduce high frequency roll off of the error-amplifier response, yielding good noise rejection in the control loop. see comp 0b /comp 1b . comp 0b , comp 1b (d6 and j6, respectively): internal loop compensation networks for channels 0 and 1, re- spectively . for the vast majority of applications , the internal , default loop compensation of the ltm4675 is suitable to apply as is, and yields very satisfactory results: apply the default loop compensation to the control loops of chan- nels 0 and 1 by simply connecting comp 0a to comp 0b and comp 1a to comp 1b , respectively. in contrast, when more specialized applications require a personal touch the optimization of control loop response, this can be easily accomplished by connecting (an) r-c network (s) from comp 0 a and/ or comp 1 a terminated to sgnd and leaving comp 0b and/or comp 1b open, as desired. ltm 4675 4675f
18 for more information www.linear.com/ltm4675 simplified block diagram decoupling requirements figure 1. simplified ltm4675 block diagram symbol parameter conditions min typ max units c inh external high frequency input capacitor requirement (5.75v v in 17v, v outn commanded to 1.000v) i out0 = 9a, 2 22f, or 3 10f i out1 = 9a, 2 22f, or 3 10f 30 44 f c outn hf external high frequency output capacitor requirement (5.75v v in 17v, v outn commanded to 1.000v) i out0 = 9a i out1 = 9a 400 400 f f t a = 25c. using figure 1 configuration. + + v in0 v out0 v in 5.75v to 17v sw 0 gnd tsns 0 v osns0 + v orb0 + v osns0 ? local high freq mlccs x1 v orb0 ? comp 0a comp 0b v out1 sw 1 gnd tsns 1b tsns 1a v osns1 [+] sgnd [v osns1 ? ] comp 1a controller signal gnd comp 1b sync asel 4675 f01 v dd25 v out0cfg v trim0cfg v trim1cfg v out1cfg f swphcfg scl 5v tolerant; pull-up resistors not shown 5v tolerant; pull-up resistors not shown 3.3v tolerant; pull-up resistor not needed sda alert wp run 0 run 1 gpio 0 gpio 1 share_clk c out0lf c out1lf c out1hf c out0hf v out0 adjustable up to 5.5v up to 9a sv in 1f 1f mt0 360nh 360nh thermal sensor thermal sensor mb0 mt1 mb1 2.2f 2.2f intv cc v dd33 v in1 c inh c inl thermal sensor analog readback signals to error amplifier power control analog section power management digital section + ? load 0 local high freq mlccs load 1 + v orb1 [+] v out1 adjustable up to 5.5v up to 9a internal comp spi slave spi master sync driver osc (32mhz) digital engine eeprom rom ram internal comp adc 3.3v tolerant; pull-up resistors not shown 3.3v tolerant; pull-up resistor not shown configuration resistors terminating to sgnd not shown ltm 4675 4675f
19 for more information www.linear.com/ltm4675 functional diagram + v in0 c inh c inl + c out0lf (computed total input current, i vino + i vin1 + i svin : read_iin) (computed channel 0 input current, i vin0 + 1/2 i svin : mfr_read_iin 0 ) (computed channel 1 input current, i vin1 + 1/2 i svin : mfr_read_iin 1 ) v in 5.75v to 17v (sv in telemetry: read_vin and mfr_vin_peak) (pwm 0 telemetry: read_duty_cycle 0 ) (pwm1 telemetry: read_duty_cycle 1 ) (i out0 telemetry: read_iout 0 and mfr_iout_peak 0 ) (i out1 telemetry: read_iout 1 and mfr_iout_peak 1 ) channel 0 thermal sensor (telemetry: read_temperature_1 0 and mfr_temperature_1_peak 0 ) channel 1 thermal sensor (telemetry: read_temperature_1 1 and mfr_temperature_1_peak 1 ) + + + ? ? ? sv in intv cc v dd33 v in1 int filter mt0 mt1 mb1 mb0 power control analog section v out0 gnd c out0hf c out1lf c out1hf v out0 adjustable up to 5.5v up to 9a v out1 adjustable up to 5.5v up to 9a sw 0 z isns0b ? v out1 gnd sw 1 z isns0b + tsns 0 ?i sns0 , channel 0 current sense signal channel 1 current sense signal, ?i sns1 channel 1 (v out1 ) voltage feedback signal (differential when terminating sgnd at load 1 as shown) ?v osns0 , differential feedback signal channel 0 (v out0 ) voltage feedback signal channel 0 current demand signal channel 1 current demand signal channel 0 internal loop compensation channel 1 internal loop compensation power controller thermal sensor (telemetry: read_temperature_2) z isns0a z comp0b tsns1b tsns1a v orb1 [+] v osns0 + v orb0 + v osns0 ? v osns1 [+] sgnd [v osns1 ? ] v orb0 ? comp 0a comp 0b scl sda wp run 0 run 1 gpio 0 gpio 1 share_clk alert comp 1a comp 1b tmux 2a 30a current mode pwm ctrl. loops, lin. regulators, dacs adc, uv/ov comparators, vco and pll, mosfet drivers and power switch logic + ? ?v osns0 v osns1 ?i sns0a ?i sns1a sv in 39 pwm0 pwm1 8:1 mux v tsns dacs, ov/uv comparators, other power management digital section digital engine, including: rom, ram, nvm and oscillator 16-bit adc spi slave r r to e/a 22pf 22pf 1nf + 20k 1nf + 20k a = 1 r r local high freq mlccs local high freq mlccs (v out0 telemetry: read_vout 0 and mfr_vout_peak 0 ) (v out1 telemetry: read_vout 1 and mfr_vout_peak 1 ) (load 0 power consumption telemetry: read_pout 0 ) load 0 z comp1b + z isns1a (load 1 power consumption telemetry: read_pout 1 ) load 1 controller signal gnd (switching frequency telemetry: read_frequency) sync v dd25 asel f swphcfg v out0cfg v trim0cfg con?guration resistors terminating to sgnd not shown v out1cfg v trim1cfg 4675 fd 14.3k 6 3.3v tolerant; pull-up resistor not shown spi master digital engine, main control eeprom ram sync driver rom program v dd33 compare i 2 c-based smbus interface with pmbus command set (10khz to 400khz compatible) channel timing management uvlo osc (32mhz) config detect sinc 3 v dd33 v dd33 10a 5v tolerant; pull-up resistors not shown 5v tolerant; pull-up resistors not shown 3.3v tolerant; pull-up resistor not needed 3.3v tolerant; pull-up resistors not shown z isns1b ? z isns1b + ltm 4675 4675f
20 for more information www.linear.com/ltm4675 test circuits test circuit 1. ltm4675 at e high v in operating range configuration, 5.75v v in 17v c inh 10f 6 c inl 150f v in 5.75v to 17v c outh0 100f 4 v out0 1v adjustable up to 9a v out1 1v adjustable up to 9a v in0 v in1 sv in v dd33 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk wp v out0 tsns 0 v orb0 + v osns0 + v osns0 ? v orb0 ? v orb1 v out1 tsns 1a tsns 1b v osns1 sgnd intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b asel f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg gnd + c outl0 opt* + c outl1 opt* + load 0 c outh1 100f 4 ltm4675 load 1 smbus interface with pmbus command set on/off control, fault management and power sequencing pwm clock synch time base synch (pull-up resistors on digital i/o pins not shown) r th1 30.1k *c outl0 , c outl1 not used in ate testing r th0 30.1k 4675 tc01 c th1 470pf c th0 470pf test circuit 2. ltm4675 at e low v in operating range configuration, 4.5v v in 5.75v r th1 30.1k *c outl0 , c outl1 not used in ate testing r th0 30.1k c th1 470pf c th0 470pf c inh 10f 6 c inl 150f v in 4.5v to 5.75v c outh0 100f 4 v out0 1v adjustable up to 9a v out1 1v adjustable up to 9a v in0 v in1 sv in v dd33 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk wp intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b asel f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg gnd + load 0 c outh1 100f 4 ltm4675 load 1 smbus interface with pmbus command set on/off control, fault management and power sequencing pwm clock synch time base synch (pull-up resistors on digital i/o pins not shown) 4675 tc02 c outl0 opt* + c outl1 opt* + v out0 tsns 0 v orb0 + v osns0 + v osns0 ? v orb0 ? v orb1 v out1 tsns 1a tsns 1b v osns1 sgnd ltm 4675 4675f
21 for more information www.linear.com/ltm4675 operation power module introduction the ltm 4675 is a highly configurable dual 9 a output standalone nonisolated switching mode step- down dc/ dc power supply with built- in eeprom nvm ( non- volatile memory ) and i 2 c - based pmbus/ smbus 2-wire serial commu- nication interface capable of 400khz scl bus speed. tw o output voltages can be regulated ( v out0 , v out1 collectively , v outn ) with a few external input and output capacitors and pull- up resistors. readback telemetry data of average input and output voltages and currents, channel pwm duty cycles, and module temperatures are continually digitized cyclically by an integrated 16-bit adc ( analog - to - digital converter ). many fault thresholds and responses are customizable. data can be autonomously saved to eeprom when a fault occurs, and the resulting fault log can be retrieved over i 2 c at a later time, for analysis. the ltm4675 provides precisely regulated output voltages between 0.6 vdc to 5.5 vdc (0.5% above 1 vdc , 5 mv below 1 vdc). the target output voltage can be set according to pin- strapping resistors ( v outn cfg and v trimn cfg pins), nvm/ register settings, and altered on the fly via the i 2 c interface. the output voltage can be modified by the user at any time with a write to pmbus vout_ command. executing this command has a typical latency less than 10ms. writes to pmbus operation have a typical latency less than 1 ms. the nvm factory- default switching frequency is 500khz and the phase- interleaving angle between its two channels is 180. channel switching frequency, phase angle, and phase relationship with respect to the falling edge of the sync pin waveform can be configured according to a pin- strap resistor ( f swphcfg pin ) and nvm / register settings though , not on the fly during regulation . the 7- bit i 2 c slave address of the module defaults to the value retrieved from mfr_ address[6:0] at power- up ( factory default: 0x 4 f ), but the least significant four bits of the address are set by resistor pin- strapping the asel pin. bits[6:4] of mfr_ address can be written and stored to eeprom. between the asel resistor pin- strap and user- configurable mfs_ address[6:4], the ltm4675 can take on any 7-bit slave address desired. with the exception of the asel pin, the module can be configured to ignore all pin- strap resistors, if desired ( see mfr_ config_ all [6]). table 1 provides a summary of ltm4675 s supported pmbus commands . for details on the supported commands , payloads and data formats see appendix c : pmbus command details. for introductory information about the pmbus specifica- tion, see appendix a: similarity between pmbus, smbus and i 2 c 2-wire interface . for information about the data communication link layer and timing diagrams, see ap- pendix b: pmbus serial digital interface. major features of the ltm4675 strictly from a dc/dc converter power delivery point of view are as follows: n up to 9a output current delivery from each of tw o integrated power stages (see front page figure) or up to 18a output, combined (see figure 27 and figure 34). n wide input voltage range: dc/dc step-down con- version from 5.75v to 17v input (see figure 60). n dc/ dc step- down conversion from 4.5v to 5.75 v input , connecting sv in to intv cc (see figure 27). n dc/ dc step - down conversion possible from less than 4.5v input when an auxiliary 5v bias supply powers sv in and intv cc (see figure 29). n output voltage range: 0.5v to 5.5v on both v out0 and v out1 . n differential remote sensing of v out 0 ( v osns 0 + / v osns0 C ). for paralleled outputs, the v osns0 + /v osns0 C pin-pair can be configured as the feedback path for both v out0 and v out1 (see figure 34 and, optionally, mfr_pwm_config[7]). n start - up into a pre - biased load without sinking current. n four ltm4675s can be paralleled to deliver up to ~70a (see figure 31). n one ltm4675 can be paralleled with three ltm4620a or ltm4630 modules to deliver up to 122a; infer rail status and telemetry of paralleled ltm4620a or ltm4630 via the sole ltm4675 (see figure 32). n discontinuous mode operation available for higher light-load efficiency (mfr_pwm_mode n [0]). n output current limit and overvoltage protection. n three integrated temperature sensors, over/under - temperature protection. n constant frequency peak current mode control. ltm 4675 4675f
22 for more information www.linear.com/ltm4675 operation n configurable switching frequency, 250khz to 1mhz; synchronizable to external clock; seven configurable channel phase interleaving settings. n internal loop compensation provided; external loop compensation can be applied, if preferred. n low profile (16mm 11.9mm 3.51mm) bga pack- age power solution requires only input and output capacitors; at most, nine pull-up resistors for open- drain digital signals; at most, six pull-down resistors to configure all possible pin-strapping options. features of the ltm 4675 that enable power system management, rail sequencing, and fault monitoring and reporting are as follows: n i 2 c - based pmbus / smbus 2- wire serial communication interface (sda, scl) with alert interrupt pin, scl clock capable of 400khz bus communication speeds with clock low extendingor 100khz, otherwise. n configurable output voltage. n configurable input undervoltage comparators (uvlo rising, uvlo falling). n configurable switching frequency. n configurable current limit. n configurable output over/ undervoltage comparators. n configurable turn-on and turn-off delay times. n configurable output ramp rise and fall times. n non- volatile configuration memory ( nvm eeprom ) to config - ure aforementioned settings, and more yielding standalone operation, if desired, and also enabling in- situ changes to the ltm4675 s configuration in embedded designs. n monitoring and reporting of telemetry data: average output and input currents and voltages , internal tem - peratures , and power stage duty cycles continuously digitized cyclically by a 16-bit adc. ? peak observed output current and voltage , input voltage , and module temperatures can be polled and cleared/reset. ? adc latency not greater than 100ms, nominal. ? option to monitor one external temperature in lieu of channel 1 ( v out 1 ) module power stage temperature . n monitoring, reporting, and configurable response to latching and non-latching individual fault and/or warning status, including but not limited to: ? output over/ undervoltages. ? input (sv in ) over/ undervoltages. ? module input and power stage output overcurrents . ? module power stage over/under temperatures. ? internal control ic overtemperature. ? communication, memory and logic (cml) faults. n fault logging upon detection of a fault condition. the ltm4675 can be configured to automatically upload a fault log to its nvm, consisting of: an uptime counter, peak observed telemetry , telemetry gathered from the six most recent rounds of cyclical adc data leading up to the detection of the fault that triggered fault log writing, and fault status associated with that adc history . n tw o configurable open-drain general purpose input/ output pins (gpio 0 , gpio 1 ), which can be used for: ? fault reporting, e.g., as a system interrupt signal. ? coordinating turn -on/off of the ltm4675 in multi- phase/multirail systems. ? propagating an unfiltered power good signal ( output of a v outn undervoltage comparator) to command turn -on/off of a downstream rail. n a write protect (wp) pin and configurable write_ protect register to protect the internal configuration of ram and nvm against unintended changes via i 2 c. n time-base interconnect (share_clk, 100khz heart- beat) for synchronization in the time domain between multiple ltm4675s. n optional external configuration resistors (rconfigs) for setting start-up output voltages , switching fre- quency and channel-to-channel phase interleaving angle. n any 7- bit slave address can be assigned to the ltm 4675 (0x4f default), configured by resistor pin strapping the asel pin and user-editable bits [7:4] of mfr_ad- dress. ltm 4675 4675f
23 for more information www.linear.com/ltm4675 operation power module configurability and readback d ata this section of the data sheet describes all the configurable features and readable data of the ltm4675 accessible via ? i 2 c . the relevant command code name ( s ) are indicated? by use of all capital letters, e.g., vin_on. refer to table 1 and appendix c: pmbus command details of this data sheet for details of the command code, payload size , data format and factory - default value . specific register bits of some registers are indicated with the use of brackets, i.e., [ and ]. the least significant bit (lsb) of a register is bit number zero, indicated by [0]. the most significant bit of a byte - long (8- bit - long ) register is bit number seven, indicated by [7]. the most significant bit (msb) of a word-long (16-bit-long) register is bit number fifteen, indicated by [15]. multiple bits of a register can be alluded to with the use of a colon, e.g., bits 2, 1 and 0 of the mfr_pwm_config register are indicated by mfr_pwm_config[2:0]. bits can take on values of 0 b or 1 b . the subscripted b suffix indicates the numbers value is in binary . values in hexadecimal are indicated with a 0x prefix. for example, decimal value 89 is indicated by 0x59 and 01011001 b (8-bit-long values), as well as 0x0059 and 0000000001011001 b (16-bit-long values). one further shorthand notion the reader will notice is the italicized n or n. n can take on a value of 0 or 1and provides an easy way to refer to registers which are paged commands, i.e., register names which have the same command code value but can be configured independently (or yield channel-specific telemetry) for channel 0 ( page 0, or 0x00) vs channel 1 (page 1, or 0x01). registers lacking an n are therefore easily identified as being global in nature, i.e., common to both channels/outputs. for example, the switching frequency setting commanded by register frequency_switch is common to both channels, and lacks n . another example: the read_vin register contains the digitized input voltage as seen at the sv in pin, and sv in is unique, i.e., common to both channels. in contrast, the nominal commanded output voltage is indicated by the register vout_command n . the n indicates that vout_command can be set dif- ferently for channel 0 vs channel 1. executing the page command (command code 0x00) with payload 0x00 sets the ltm4675 to write/read data pertaining to channel 0 in all subsequent i 2 c transactions until the page is changed. executing the page command with payload 0x01 sets the ltm4675 to write/read data pertaining to channel 1 in all subsequent i 2 c transactions until the page is changed. executing the page command with payload 0xff sets the ltm4675 to write data pertaining to channels 0 and ?1 in all subsequent i 2 c write transactions until the page is changed. reads from and writes to global registers do not require setting the page to 0xff. reads from channel- specific (i.e., non-global) registers when the page is set to 0xff result in the ltm4675 reporting the value on page 0x00 (i.e., channel 0-specific data). the list below itemizes aspects of the ltm4675 relating to power supply functions that are configurable by i 2 c communicationsprovided the state of the wp (write protect ) pin and the write _ protect register value permit the i 2 c writesand by eeprom settings: n output start - up voltages ( vout _ command n ), the maximum commandable output voltages ( vout _ max n ), output margin high ( vout _ margin _ high n ) and margin low ( vout_ margin_ low n ) command voltages, and output over/ undervoltage warning and fault thresholds ( vout _ ov _ warn _ limit n , vout _ ov _ fault _ limit n , vout _ uv _ warn _ limit n , and vout _ uv _ fault _ limit n ). additionally, these values can be configured at sv in power- up according to resistor- pin strapping of the v out0 cfg , v trim0 cfg , v out1 cfg and/ or v trim1 cfg pins, provided mfr_ config_ all[6] = 0 b . n output voltages, on the fly, including transition rate (?v/?t), vout_transition_rate n either by i 2 c writes to the vout_command n , vout_margin_ high n , or vout_margin_low n registers, and/or to the operation n register. n input undervoltage-lockout, rising (vin_on) and input undervoltage lockout, falling (vin_off), based on the sv in pin voltage. n switching frequency ( frequency _ switch ) and channel phase- interleaving angle ( mfr_ pwm_ config [2:0]). however, these parameters can be changed via i 2 c communications only when the ltm4675s channels are off, i.e., not switching. the ltm4675 synchronizes ltm 4675 4675f
24 for more information www.linear.com/ltm4675 operation its switching frequency to a clock signal supplied to its sync pin when mfr_config_all[4]=1 b . these parameters can be configured at sv in power - up according to resistor-pin strapping of the f swphcfg pin, provided mfr_config_all[6] = 0 b . n output voltage turn-on and turn-off sequencing and associated watchdog timers, namely: ? output voltage turn - on delay time ( the time delay from the ltm4675 being commanded to turn on, e.g., by the run n pin toggling from logic low to high, before switching action commences. ton_ delay n ). ? output voltage soft - start ramp - up time ( ton _ rise n ). ? the amount of time (ton_max_fault_limit n ) permitted to elapse after the ltm 4675 is commanded to turn on, e.g., by the run n pin toggling from logic low to high, after which, if the output voltage fails to exceed the output undervoltage fault threshold (vout_uv_fault_limit n ), the ltm4675s output (v outn ) is declared to have not come up in a timely manner. ? the ltm4675 s response to any such afore- mentioned ton _ max _ fault _ limit n event (ton_max_fault_response n ). ? output voltage soft- stop ramp- down time (toff_ fall n ). ? output voltage turn - off delay time ( the time delay from the ltm4675 being commanded to turn off, e . g ., by the run n pin toggling from logic high to low, before switching action ceases. toff_ delay n ). ? when commanded to turn off its output or, when turning off its output in response to a fault configuring whether the ltm4675's output (v outn ) becomes high impedance ( high - z or three stateturning off both mtn and mbn in the power stage). (immediate off, on_off_config n [0] = 1 b vs configuring the output voltage to be ramped down according to toff _ fall n and / or toff _ delay n settings, on_off_config n [0] = 0 b ). ? the amount of time (toff_max_warn_limit n ) permitted to elapse after the ltm4675 is supposed to have turned off its output, i.e., at the end of the period dictated by toff_ fall n , after which, if the output voltage has not fallen below 12.5% of the former target voltage of regulation, the ltm4675s output (v outn ) is declared to have not powered down in a timely manner. n configurable output voltage restart time. subsequent to the run n pin being pulled low, the ltm4675 pulls run n logic low, itself, and the output cannot be restarted until a minimum time has elapsed the restart delay time. this delay assures proper sequencing of all system rails. the minimum restart delay processed by the ltm4675 is the longer of ( toff_ delay n + toff_ fall n + 136ms) vs the commanded mfr_ restart_ delay n register value. at the end of this delay, the ltm4675 releases its run n pin. n configurable fault- hiccup retry delay time. when a fault occurs in which the ltm4675 s fault response behavior to that fault is to reattempt power- up of its output voltage after said fault ceases to be present ( e . g ., infinite retry ), the delay time for the ltm4675 to re- engage switching action is the longer of the mfr_ retry_ delay n time vs the time required for the output to decay below 12.5% of the formerly commanded output voltage value ( unless this lattermost criteria , i . e ., requiring the output to decay below 12.5% is negated by the setting of mfr_ chan_ con- fig n [0] to 1 b which is the ltm4675 s factory - nvm default setting). n output over/undervoltage fault responses (vout_ov_ fault _ response n , vout _ uv_ fault _ response n ). n time - averaged current limit warning and instantaneous peak ( cycle - by - cycle ) fault thresholds , and fault response (iout_oc_warn_limit n , iout_oc_fault_limit n , iout_oc_fault_response n ). n channel (v out0 , v out1 ) overtemperature warning and fault thresholds , and fault response ( ot_ warn_ limit n , ot_fault_limit n , ot_fault_response n ). n channel ( v out0 , v out1 ) undertemperature fault thresholds and fault response ( ut _ fault _ limit n , ut_fault_response n ). n input overvoltage fault threshold and response ( vin_ ov_ fault_ limit, vin_ ov_ fault_ response ), based on the sv in pin voltage. ltm 4675 4675f
25 for more information www.linear.com/ltm4675 operation n input undervoltage warning threshold ( vin _ uv _ warn _ limit) based on the sv in pin voltage. n module input overcurrent warning threshold (iin_oc_warn_limit) the control ic within the ltm4675 module ceases switching action if control ic temperature exceeds 160c (note 12). the control ic resumes operation after a 10c cool-down hysteresis. note that these typical parameters are based on measurements in a lab oven and are not production tested. this overtemperature protection is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operat- ing junction temperature may impair device reliability or permanently damage the device. time- averaged and peak readback d ata time -averaged telemetry readback data accessible via i 2 c communications follow: n channel output current ( read _ iout n ) and peak observed value of read_iout n (mfr_iout_peak n ). n channel output voltage ( read_ vout n ) and peak observed value of read_vout n (mfr_vout_peak n ). n channel output power (read_pout n ). n channel input current (mfr_read_iin n ) and module input current (read_iin). n channel temperatures ( read_ temperature _1 n ) and peak observed values of read_temperature_1 n (mfr_temperature_1_peak n ). n control ic temperature ( read _ temperature _2) and peak observed value (mfr_temperature_2_peak). n input voltage (read_vin), based on the voltage of the sv in pin, and peak observed value of read_vin (mfr_vin_peak). n channel topside power mosfet (mtn) duty cycle (read_duty_cycle n ) digitized cyclical telemetry is available at a 10hz update rate, typical. through the use of the mfr_adc_control command, some signals of interest can be digitized more frequentlyup to a 125hz update rate, typical. availability of newly digitized telemetry data can be made known via the mfr_adc_telemetry_ status command. digitized cyclical telemetry is available at a 10hz update rate, typical. through the use of the mfr_adc_control command, some signals of interest can be digitized more frequentlyup to a 125hz update rate, typical. availability of newly digitized telemetry data can be made known via the mfr_adc_telemetry_ status command. peak observed values of telemetry readback data can be cleared with the mfr_clear_peaks i 2 c command, provided the write_protect register value permits it. ( executing mfr _ clear _ peaks can be performed regard - less of the state of the wp pin.) details on the ltm4675s fault log feature follow: n fault logging is enabled when mfr_ config_ all [7] = 1 b . n a fault log is present in nvm when status_mfr_ specific n [3]reports 1 b , which is propagated to the mfr bit (bit 12) of the status_word register. n retrieving fault log data, if present, is performed with the mfr_fault_log command. 147 bytes of data are retrieved using the pmbus-defined variant to the smbus block read protocol. n the fault log contents in nvm, if present, are cleared by executing the mfr_fault_log_clear command. n the fault log will not be written if a fault log is already present in nvm. n the ltm4675 can be forced to write a fault log to its nvm by executing the mfr_fault_log_store command; the ltm4675 will behave as if a channel faulted off. note the command is nacked and a cml fault is reported if a fault log is already present at the time of executing mfr_fault_log_store. when an external stimulus pulls the ltm 4675 s gpio n pin ( s ) logic low , the respective channel ( v out n ) ei - ther: takes no action on it, i . e ., ignores it completely if mfr_ gpio_ response n = 0x 00; or, turns off immediately, ltm 4675 4675f
26 for more information www.linear.com/ltm4675 operation i . e ., the power stage ( s ) become high impedance ( inhibited ) if mfr_ gpio_ response n = 0xc0. the mfr_gpio_ propagate n register contents config- ure which fault(s) cause the ltm4675 to pull its gpio n pin(s) logic low. i 2 c communications are originated by the user s ( system s ) i 2 c master device. writes/reads to/from channel 0 of the ltm4675 (v out0 : page 0x00), to/from channel 1 of the ltm4675 (v out1 : page 0x01), or writes to both channels 0 and 1 of the ltm4675 (v out0 and v out1 : page 0xff) are possible. the target channel(s) of interest are selected by the i 2 c master by executing the page command and sending the appropriate argument (0x00, 0x01, 0xff) in the payload. the page command is unrestricted, i.e., not affected by the wp pin or write_protect register settings. the ltm4675 always responds to its global slave ad- dresses, 0x5a and 0x5b. commands sent to the global address 0x5a act the same as if the page command were set to 0xff, i.e., received commands are written to both channels simultaneously. commands sent to the global address 0x5b are applied to the page active at the time of the global address transaction, i . e ., allows channel- specific command of all ltm4675 devices on the bus. i 2 c commands not listed above that relate to fault status and eeprom nvm operations follow. writing of the following is possible provided the state of the wp (write protect) pin and the write_protect register value permits the i 2 c writes: n soliciting (reading) module fault status and clearing ( writing ) module fault status ( clear _ faults , status _ byte n , status_word n , status_vout n , status_ iout n , status _ input , status _ temperature n , status _ cml [ communications , memory , and / or logic ], and status _ mfr _ specific n [ miscellaneous ]). n storing the ltm 4675 s user - writable ram register data to the eeprom nvm (store_user_all). n an alternate means to the store_ user_ all command to directly erase and write the ltm4675 s eeprom contents , protected by unlock keys, to facilitate programming of the ltm4675 eeprom in environments such as ict ( in- circuit test) and bulk programming by, e . g ., embedded hardware or by the ltpowerplay gui. also, a means to directly read the ltm4675 eeprom contents ( mfr_ ee_ unlock, mfr_ ee_ erase, mfr_ ee_ data ). n instigating a soft reset of the ltm4675 without power- cycling sv in power (mfr_reset). the mfr_reset command triggers the download of eeprom nvm data to ram registers, as if sv in power had been cycled. n forcing a download of eeprom nvm data to ram registers ( restore _ user _ all ). this is indistinguishable from executing mfr_reset. other data that can be obtained from the ltm4675 via i 2 c communications are as follows: n soliciting the ltm4675 for its pmbus capabilities, as defined by pmbus ( capability): ? pec (packet error checking). note, the ltm4675 requires valid pec in i 2 c communications when mfr_ config _ all[2] = 1 b . the nvm factory - default configuration is mfr_config_all[2] = 0 b , i.e., pec not required. ? i 2 c communications can be supported at up to 400khz scl bus speed. note, clock low extending (clock stretching) must be enabled on the ltm4675 to ensure robust communications above 100khz scl bus speeds, i.e., mfr_config_all[1] = 1 b . the nvm factory-default configuration is mfr_config_ all[1] = 0 b , i.e. clock stretching is disabled. ? the ltm4675 has an smbalert ( alert) pin and does support the smbus ara (alert response ad- dress) protocol. n soliciting the module for the maximum output voltage it can be commanded to produce (mfr_vout_max n ). n soliciting the device for the data format of its output voltage-related registers (vout_mode n ). n soliciting the device for the revisions of pmbus specifica- tions that it supports ( part i : rev. 1.2; part ii: rev 1.2). n soliciting the device for the identification of the manufacturer of the ltm4675, ltc (mfr_id) and the manufacturer code representing the ltm4675 and revision, 0x47ax (mfr_special_id). ltm 4675 4675f
27 for more information www.linear.com/ltm4675 operation n soliciting the device for its part number, ltm4675 (mfr_model). n soliciting the module for its serial umber (mfr_serial). n the digital status of the ltm4675s i/o pads and validity of the adc (mfr_pads) and wp pin status (mfr_common[0]). the following list indicates other aspects of the ltm4675 relating to power system management and power sequencing that are configurable by i 2 c communications provided the state of the wp (write protect) pin and the write _ protect register value permit the i 2 c writes and by eeprom settings: n providing multiple means to read/write data directly to a particular channel of the ltm4675 by assigning additional slave address for channels 0 and 1 ( mfr_ rail _ address n ), the benefit of which is that it reduces page command usage and associated i 2 c traffic. it also facilitates altering the same register of multiple ltm4675 in unison without invoking the pmbus group command protocol. see also page_plus_read and page_plus_write. n configuring the output voltage to be on or off by means other than the run n pin ( on_ off _ config n [3], opera - tion commands). n configuring whether the ltm4675 performs a clear _ faults command upon itself when either run n pin toggles from logic low to logic high . (mfr_config_all[0]). n configuring whether the ltm4675 pulls run n logic low when the ltm4675 is commanded off by other means (mfr_chan_config n [4]). n configuring the response of the ltm4675 when it is commanded to turn on its output prior to the completion of processing toff_delay n and toff_fall n power- down sequencing (mfr_chan_config n [3]). n configuring whether the ltm4675 s output is disabled when share_clk is held low (mfr_chan_ config n [2]). n configuring whether the alert pin is pulled low when gpio n is pulled low by external stimulus (mfr_chan_ config n [1]). n setting the value of the mfr_iin_offset n registers, representing an estimate of the current drawn by the sv in pin. the sv in pin current is not measured by the ltm4675 but the mfr_iin_offset n is used in computing and reporting channel and total module input currents (mfr_read_iin n , read_iin). n three words (six bytes) of the ltm4675s eeprom that are available for storing user data . (user_data_03 n , user_data_04). n invoking or releasing several levels of i 2 c write protection (write_protect). n configuring the bus timeout for 255 ms ( mfr _ config _ all[3]=1 b ) if the host needs more time to complete i 2 c transactions. n determining whether the user-editable ram register values are identical to the contents of the user nvm (mfr_compare_user_all). n setting the programmable output voltage range of v out to a narrower range (0.5v to 2.75v) in order to achieve a higher resolution of v out adjustment than is available by default ( mfr_ pwm_ mode n [1]). mfr_ pwm_ mode cannot be changed on the fly; switching action must be off. note that altering the v out range alters the gain of the control loop and may therefore require loop compensation to be adjusted. n altering the temperature coefficient of the ltm4675s current sensing elements, if needed (mfr_iout_cal_ gain_tc n ) (uncommon to alter this parameter from its nvm- factory default setting). n altering the gain or offset of the power stage sensors ( mfr _ temp _1_ gain n and mfr _ temp _1_ offset n ) or that of the external temperature sensor, when an external temperature sensor is used on the tsns 1a pin. (uncommon to alter this parameter from its nvm- factory default setting). ltm 4675 4675f
28 for more information www.linear.com/ltm4675 operation n configuring whether the ltm4675 pulls share_clk logic low when sv in has fallen outside its uvlo thresholds ( mfr _ pwm _ config [4]). mfr _ pwm _ config cannot be changed on the fly; switching action must be off (uncommon to alter this parameter from its nvm- factory default setting). n configuring whether the ltm4675s output voltage digital servos are active vs disengaged (mfr_pwm_ mode n [6]. uncommon to alter this parameter from its nvm- factory default settings). n configuring whether the ltm4675 s current limit range is set to high range vs low range. (mfr_pwm_ mode n [7]. not recommended to alter this parameter from its nvm- factory default settings). remaining ltm4675 status that can be queried over i 2 c communications follow: n access to three hand - shaking status bits ( mfr _ com - mon[6:4]) to ease implementation of pmbus busy protocols, i.e., enabling fast and robust system level communication through polling of these bits to infer ltm4675s readiness to act on subsequent i 2 c writes. ( see pmbus communication and command processing , in the applications information section.) n providing a means to determine whether the ltm4675 nvm download to ram has occurred ( nvm initialized , mfr_common[3]). n providing a means other than ara protocol to de- termine whether the ltm4675 is pulling alert low (mfr_common[7]). n detecting a share _ clk timeout event (mfr_common[1]). n verifying or altering the slave address of the ltm4675 (mfr_address). power module overview a dedicated remote - sense amplifier precisely kelvin - senses v out0 s load via the differential pin- pair formed by v osns0 + and v osns0 C . v out0 can be commanded to between 0.5vdc and 5.5vdc. v out1 is sensed via the pin-pair formed by v osns1 and signal ground of the modules sgnd. v out1 can be commanded to between 0.5vdc and 5.5vdc. output voltage readback telemetry is available over i 2 c (read_vout n registers). peak output voltage readback telemetry is accessible in the mfr_read_vout_peak n registers. if v osns0 C exceeds v osns + , no phase reversal of the differentially-sensed output voltage feedback signal occurs ( note 12). similarly , no phase reversal occurs when sgnd exceeds v osns1 (note 12). for added flexibility, the v osnso + /v osnso C feedback pins can be configured as the control loop feedback path for both v out0 and v out1 by setting mfr_pwm_config[7]=1 b . (see figure 34). the typical application schematic is shown in figure 60 on the back page of this data sheet. the ltm4675 can operate from input voltages between 5.75 v and 17 v ( see front page figure ). in this con - figuration , intv cc mosfet driver and control ic bias is generated internally by an ldo fed from sv in to produce 5v at up to 100ma peak output current. additional internal ldos 3.3v (v dd33 ), derived from intv cc , and 2.5v (v dd25 ), derived from v dd33 bias the ltm4675s digital circuitry . when intv cc is connected to sv in , the ltm4675 can operate from input voltages between 4.5v and 5.75v (see figure 27). control ic bias (sv in ) is routed independent of the inputs to the power stages (v in0 , v in1 ); this en- ables step-down dc/dc conversion from less than 4.5v input (see figure 29), so long as auxiliary power (4.5v ~ 17v) is available to bias the control ic appropriately. furthermore, the inputs of the two power stages are not connected together internal to the module; therefore, dc/ dc step - down conversion from two different source power supplies can be performed. per note 6 of the electrical characteristics section, the output current may require derating for some operating scenarios. detailed derating guidance is provided in the applications information section. ltm 4675 4675f
29 for more information www.linear.com/ltm4675 operation the ltm 4675 contains dual integrated constant frequency current mode control buck regulators (channel 0 and channel 1) whose built-in power mosfets are capable of fast switching speed. the factory nvm-default switching frequency clocks sync at 500khz, to which the regula- tors synchronize their switching frequency. the default phase-interleaving angle between the channels is 180. a pin-strapping resistor on f swphcfg configures the fre- quency of the sync clock (switching frequency) and the channel phase relationship of the channels to each other and with respect to the falling edge of the sync signal. (not all possible combinations of switching frequency and phase-angle assignments are settable by resistor pin programming; see table 4. configure the ltm4675s nvm to implement settings not available by resistor-pin strapping.) when a f swphcfg pin-strap resistor sets the channel phase relationship of the ltm4675s channels, the sync clock is not driven by the module; instead, sync becomes strictly a high impedance input and channel switching frequency is then synchronized to sync provided by an externally-generated clock or sibling ltm4675 with pull-up resistor to v dd33 . switching frequency and phase relationship can be altered via the i 2 c interface , but only when switching action is off, i.e., when the module is not regulating either output. see the applications information section for details. internal feedback loop compensation for regulator 0 is available by connecting comp 0a to comp 0b . (for regula- tor ?1, the connection is from comp 1a to comp 1b .) with current mode control and internal feedback loop com- pensation, the ltm4675 module has sufficient stability margins and good transient performance with a wide range of output capacitorseven all-ceramic mlccs. table 20 provides guidance on input and output capacitors recommended for many common operating conditions. the linear technology module power design tool is available for transient and stability analysis. furthermore, expert users who prefer to not make use of the modules internal feedback loop compensationbut instead, tailor the feedback loop compensation specifically for his/her applicationmay do so by not connecting comp n a to comp n b : the personalized loop compensation network can be applied externally, i.e., from comp n a to sgnd, and leaving comp n b open circuit. the ltm4675 has two general purpose input/output pins, named gpio 0 and gpio 1 . the behavior of these pins is configurable via registers mfr _ gpio _ propagate n and mfr_gpio_response n . the gpio n pins are high impedance during nvm-download-to-ram initialization. these pins are intended to perform one of two primary functions, or a hybrid of the two: behave as open- drain, active low fault/warning indicators; and/or, behave as auxiliary run pins for their respective v out s. in the former case, the pins can be configured as interrupt pins , pulling active low when output under/overvoltage, input under/ overvoltage, input/output overcurrent, overtemperature, and/or communication, memory or logic (cml) fault or warning events are detected by the ltm4675. factory nvm-default settings configure the ltm4675 for the latter case, enabling the gpio n to be bussed to paralleled siblings ( paralleled ltm4675 channels and/ or modules ), for purposes of coordinating orderly power- up and power - down, i . e ., in unison. the ltm4675 dc/ dc regulator does not feature a traditional power good (pgood ) indicator pin to indicate when the output voltage is within a few percent of the target regulation point. however, the gpio n pin can be configured as a pgood indicator. if used for event- based sequencing of downstream rails, configure gpio n as the unfiltered output of the vout_ uv_ fault_ limit n comparator , setting bit 12 of mfr _ gpio _ propagate n to 1 b ; do not set bits 9 and 10 of mfr_ gpio_ propagate n for this purpose, since the propagation of power good in those latter instances is subject to supervisor filtering and comparator latency. if it is necessary to have the desired pgood polarity appear on the gpio n pin immediately upon sv in power- up given that the pin will initially be high impedance, until nvm contents have downloaded to ram a pull- down schottky diode is needed between the run n pin of the ltm4675 and the respective gpio n pin . (see figure 2 ). if the gpio n pin is configured as a pgood indicator, the mfr_ gpio_ response n must be set to ignore (0x 00), or else the ltm4675 cannot start up due to the latch- off conditions imposed. the run n pin is a bidirectional open-drain pin. this means it should never be driven logic high from a low impedance source . instead , simply provide a 10k pull- up resistor from the run n pins to v dd33 . the ltm4675 pulls its run n pin logic low during nvm-download-to-ram initialization, ltm 4675 4675f
30 for more information www.linear.com/ltm4675 operation when sv in is below the commanded undervoltage lockout voltage ( vin _ on , rising and vin _ off , falling ), and subsequent to external stimulus pulling run lowfor a minimum time dictated by mfr_restart_ delay n . bussing the respective run n and gpio n pins to sibling ltm4675 modules enables coordinated power - up/ power - down to be well orchestrated , i.e., performing turn-on and turn-off in a unified fashion. when run n exceeds 2v, the ltm4675 initially idles for a time dictated by the ton_delay n register. after the ton_delay n time expires, the module begins ramping up the respective control loop s internal reference , starting from 0v. in the absence of a pre-biased v outn condition, the output voltage is ramped linearly from 0v to the commanded target voltage, with a ramp-up time dictated by the ton_rise n register. in the presence of a pre-biased v outn condition, the output voltage is brought into regulation in the same manner as aforementioned, with the exception that inductor current is prevented from going negative (the modules controller is operated in discontinuous mode operation during start-up). in both cases , the output voltage reaches regulation in a consistent time, as measured with respect to run n toggling high. see start- up oscilloscope shots in the typical performance characteristics section. pulling the run n pin below 1.4v turns off the dc/dc converter , i . e ., forces the respective regulator into a shutdown state . factory nvm - default settings configure the ltm 4675 to turn off its power stage mosfets immediately , thereby becoming high impedance . the output voltage then decays according to whatever output capacitance and load impedance is present . alternatively , nvm / register settings can configure the ltm4675 to actively discharge v outn when run n is pulled logic low, according to prescribed toff_delay n delay and toff_ fall n ramp-down times. see the applications information section for details. the ltm4675 does not feature an explicit, analog track pin. rail-to-rail tracking and sequencing is handled digitally, as explained previously. bussing the open-drain share_clk pins of all ltm4675s (and providing a pull-up resistor to v dd33 ) provides a means for all ltm4675s in the system to synchronize their time-base (or heartbeat) to the fastest share_clk clock . sharing the heartbeat amongst all ltm 4675 ensures that all rails are sequenced according to expectations; it negates timing errors that could otherwise materialize due to share_clk (time-base) tolerance and part-to- part variation. electrically connect adjacent pins i sns 0 a + to i sns 0 b + ; i sns 0 a C to i sns0b C ; i sns1a + to i sns1b + ; and i sns1a C to i sns01b C . current sense information is derived from across the power inductors ( i sns n b + / i sns n b C pin - pairs ) internal to the ltm4675 and made available to the internal control ics current control loops and adc sensors ( i snsn a + / i snsn a C ) by the aforementioned connections. output current readback telemetry is available over i 2 c (read_iout n registers). peak output current readback telemetry is available in the mfr_read_iout_peak n registers. output power readback is computed by the ltm4675 according to: read_pout n = read_vout n ? read_iout n alternating excitation currents of 2 a and 30 a are sourced from the tsns 1a pin. connecting tsns 1a to tsns 1b , temperature sensing of the channel 1 power stage is realized by the ltm4675 digitizing the voltages that appear at the pnp transistor temperature sensor that resides at the tsns 1b pin. analogous activity occurs on the tsns 0 figure 2. event ( voltage) based sequencing ltm4675 voltage based sequencing by cascading gpio n pins into run n pins (mfr_gpio_propagate = xxx1x00xx00xxxxx b and mfr_gpio_response = 0x00) gpio 0 = v out0_uvuf gpio 1 = v out1_uvuf run 1 note: resistor or rc pull-ups on run n and gpio n pins not shown *optional signal schottky diode. only needed when accurate pgood (power good) indication is requred by the system/user immediately at sv in power up run 0 start ltm4675 4675 f02 run 0 gpio 0 = v out0_uvuf gpio 1 = v out1_uvuf to next channel in the sequence run 1 * * * * ltm 4675 4675f
31 for more information www.linear.com/ltm4675 operation node, from which channel 0 power stage temperature is derived. the ltm4675 performs what is known in the industry as delta vbe (?vbe) computations and makes channel (power stage) temperature telemetry available over i 2 c ( read _ temperature _1 n ). the junction temperature of the control ic within the ltm4675 is also available over i 2 c (read_temperature_2). observed peak channel temperatures can be read back in registers read_mfr_temperature_1_peak n . observed peak temperature of the control ic can be read back in register mfr_read_temperature_2_peak. for a fixed load current, the amplitude of the current sense information changes over temperature due to the temperature coefficient of copper ( inductor dcr ), which is approximately 3900ppm/c. this would introduce signifi- cant current readback error over the operating range of the module if not for the fact that the ltm4675s temperature readback information is used in conjunction with the per - ceived current sense signal to yield temperature -corrected current readback data. if desired, it is possible to use only the temperature readback information derived by the tsns 0 pin to yield temperature- corrected current readback data for both channels 0 and 1. this frees up the channel 1 temperature sensor to monitor a temperature sensor external to the ltm4675. this is achieved by setting mfr_ pwm_ mode 0 [4] = 1 b ( the nvm- factory default value is 0 b ). this degrades the current readback accuracy of channel 1more so when channel 0 and channel ?1 are not paralleled outputs . however , the tsns 1 a pin becomes available to be connected to an external diode- connected small- signal pnp transistor ( such as 2 n 3906) and 10nf x 7 r capacitor, i . e ., an external temperature sensor, whose temperature readback data and peak value are available over i 2 c ( read_ temperature_1 1 , mfr_ read_ temperature _1_peak 1 ). implementation of the aforementioned is as follows : (1) local to the ltm4675, electrically connect a 10 nf x 7 r capacitor directly from tsns 1 a to sgnd; (2) differentially route a pair of traces from the ltm4675' s tsns 1 a and sgnd pins to the target pnp transistor; (3) electrically connect the emitter of the pnp transistor to tsns 1 a ; (4) electrically connect the col- lector and base of the pnp transistor to sgnd. power stage duty cycle readback telemetry is available over i 2 c (read_duty_cycle n registers). computed channel input current readback is computed by the ltm4675 as: mfr_read_iin n = read_duty_cycle n ? read_iout n + mfr_iin_offset n computed module input current readback is computed by the ltm4675 as: read_iin = mfr _read_iin 0 + mfr _read_iin 1 where mfr_iin_offset n is a register value representing the sv in input bias current. the sv in current is not dig- itized by the module. the factory nvm-default value of mfr _ iin _ offset n is 29.56 ma , representing the contribution of current drawn by each of the modules channels on the sv in pin, when the power stages are operating in forced continuous mode at the factory - default switching frequency of 500khz. see table 8 in the applications information section for recommended mfr_iin_offset n setting vs switching frequency. the aforementioned method by which input current is calculated yields an accurate current readback value even at light load currents, but only as long as the module is configured for forced continuous operation (nvm-factory default). sv in and peak sv in readback telemetry is accessible via i 2 c in the read _ vin and mfr _ vin _ peak registers , respectively . the power stage switch nodes are brought out on the sw n pin for functional operation monitoring and for optional installation of a resistor-capacitor snubber circuit (termi- nated to gnd) for reduced emi. the ltm4675 features a write protect (wp) pin. if wp is open circuit or logic high , i 2 c writes are severely restricted : only i 2 c writes to the page, operation , clear_ faults, mfr_clear_peaks, and mfr_ee_unlock commands are supported, with the exception that individual fault bits can be cleared by writing a 1 b to the respective bits in the status_* registers. register reads are never restricted. not to be confused with the wp pin, the ltm4675 features a write_protect register, which is also used to restrict i 2 c writes to register contents. refer to appendix c: pmbus command details for details. the wp pin and the write_protect register provide a level of protection against accidental changes to ram and eeprom contents . ltm 4675 4675f
32 for more information www.linear.com/ltm4675 operation the ltm4675 supports all possible 7-bit slave addresses. the factory nvm-default slave address is 0x4f. the lower four bits of the ltm4675s slave address can be altered from this default value by connecting a resistor from the asel pin to sgnd. see table 5 in the applications information section for details. bits[6:4] can be altered by writing to the slave_address command. the value of the slave_address command can be stored to nvm, however, the lower four bits of the slave_address is always dictated by the asel resistor pin-strap setting. up to four ltm4675 modules (8 channels) can be par- alleled , suitable for powering ~70 a loads such as cpus and gpus . ( see figure 31 ) the ltm 4675 can be paralleled with ltm4620a or ltm4630 modules, as well (see figure 32 and figure 33). eeprom the ltm4675s control ic contains an internal eeprom (non-volatile memory , nvm) to store configuration set- tings and fault log information. eeprom endurance re- tention and mass write operation time are specified in the electrical characteristics and absolute maximum ratings sections. write operations at t j < 0 c or at t j > 85 c are possible although the electrical characteristics are not guaranteed and the eeprom retention characteristics may be degraded. read operations performed at junction temperatures between C40c and 125c do not degrade the eeprom. the fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log-specific eeprom locations (partitions). if occasional writes to these regis- ters occur above 85c junction, the slight degradation in the data retention characteristics of the fault log does not undermine the usefulness of the function. it is recommended that the eeprom not be written when the control ic die temperature is greater than 85c. if the die temperature exceeds 130c, the ltm4675s control ic disables all eeprom write operations. eeprom write operations are subsequently re-enabled when the die temperature drops below 125c. the degradation in eeprom retention for temperatures >125c can be approximated by calculating the dimen- sionless acceleration factor using the following equation: af = e ea k ? ? ? ? ? ? ? 1 t use + 273 C 1 t stress + 273 ? ? ? ? ? ? ? ? ? ? ? ? where: af = acceleration factor ea = activation energy = 1.4ev k = 8.617 ? 10 C5 ev/k t use = 125c specified junction temperature t stress = actual junction temperature in c example: calculate the effect on retention when operating at a junction temperature of 135c for 10 hours. t stress = 130c t use = 125c af= e [(1.4/8.617 ? 10 C5 ) ? (1/398 C 1/403)] = 1.66 the equivalent operating time at 125c = 16.6 hours. thus the overall retention of the eeprom was degraded by 6.6 hours as a result of operating at a junction tempera- ture of 130c for 10 hours. the effect of the overstress is negligible when compared to the overall eeprom retention rating of 87,600 hours at a maximum junction temperature of 125c. the integrity of the eeprom is checked with a crc calculation each time its data is read, such as after a power-on reset or execution of a restore_user_all or mfr _ reset command . if crc error occurs , the mfr bit is set in the status _ byte and status _ word commands . the nvm crc error bit in the status_mfr_specific command is set and the alert and run pins are pulled low disabling the output as a safety measure. the device will only respond at special address 0x7c or global ad- dresses 0x5a and 0x5b. ltm 4675 4675f
33 for more information www.linear.com/ltm4675 operation crc protection the integrity of the eeprom memory is checked after a power - on reset . a crc error will prevent the controller from leaving the off state. if a crc error occurs, the cml bit is set in the status _ byte and status _ word commands , the appropriate bit is set in the status_mfr_specific command, and the alert pin will be pulled low. eeprom repair can be attempted by writing the desired configuration to the controller and executing a store _ user_ all command followed by a clear_ faults command. the ltm4675 manufacturing section of the eeprom is mirrored. the ltm4675 has the ability to operate if either one of the two sections of the manufacturing sec- tion of the eeprom configuration becomes corrupted. if a discrepancy is detected, the nvm crc fault in the status _mfr _specific command is set . if this bit remains set after being cleared by issuing a clear_ faults or writing a 1 to this bit, an irrecoverable internal fault has occurred. there are no provisions for field repairing un- recoverable eeprom faults in the manufacturing section. serial interface the ltm4675 serial interface is a pmbus compliant slave device and can operate at any frequency between 10khz and 400khz. the address is configurable using either the eeprom or an external resistor divider. in addition the ltm4675 always responds to the global broadcast address of 0x5a (7 bit) or 0x5b (7 bit). address 0x5a is not paged and is performed on both channels. 0x5b respects the page command. because address 0x5a does not support page, it can not be used for any paged reading commands. the serial interface supports the following protocols defined in the pmbus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word and 7) read block 8) page_plus_read, 9) page _ plus _ write 10) smbalert _ mask read , 11) smbalert_mask write. all read operations will return a valid pec if the pmbus master requests it. if the pec_required bit is set in the mfr_config_all command, the pmbus write operations will not be acted upon until a valid pec has been received by the ltm4675. communication protection pec write errors (if pec_required is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a cml fault. the cml bit is set in the status_byte and status_word commands , the appropriate bit is set in the status_cml command, and the alert pin is pulled low. device addressing the ltm4675 offers four different types of addressing over the pmbus interface , specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ara). global addressing provides a means of the pmbus master to address all ltm4675 devices on the bus. the ltm4675 global address is fixed 0 x 5 a (7 bit ) or 0 xb 4 (8 bit ) and cannot be disabled. commands sent to the global address act the same as if page is set to a value of 0 xff. commands sent are written to both channels simultaneously. global command 0 x 5 b (7 bit ) or 0 xb 6 (8 bit ) is paged and allows channel specific command of all ltm4675 devices on the bus. other lt c device types may respond at one or both of these global addresses; therefore do not read from global addresses. rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage ( polyphase ? ). while similar to global addressing, the rail address can be dynamically assigned with the paged mfr_ rail_ address command, allowing for any logical grouping of channels that might be required for reliable system control. do not read from rail addresses because multiple lt c devices may respond. device addressing provides the standard means of the pmbus master communicating with a single instance of an ltm4675. the value of the device address is set by a combination of the asel0 and asel1 configuration pins and the mfr_address command. when this addressing means is used , the page command determines the channel being acted upon. device addressing can be disabled by writing a value of 0x80 to the mfr_address. all four means of pmbus addressing require the user to employ disciplined planning to avoid addressing conflicts. communication to ltm4675 devices at global and rail ad- dresses should be limited to command write operations. ltm 4675 4675f
34 for more information www.linear.com/ltm4675 operation fault detection and handling a variety of fault and warning reporting and handling mechanisms are available. fault and warning detection capabilities include: n input ov/ fault protection and uv warning n average input oc warn n output ov/uv fault and warn protection n output oc fault and warn protection n internal and external overtemperature fault and warn protection n external undertemperature fault protection n cml fault (communication, memory or logic) n external fault detection via the bidirectional gpion pins. in addition , the ltm 4675 can map any combination of fault indicators to their respective gpio n pin using the propagate gpio n response commands, mfr_gpio_propagate n . typical usage of a gpio pin is as a driver for an external crowbar device, overtemperature alert, overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands . alternatively, the gpio n pins can be used as inputs to detect external faults downstream of the controller that require an immediate response. the gpio 0 and/or gpio 1 pins can also be configured as power good outputs. power good indicates the controller output is within the ov/uv fault thresholds. at power-up the pin will initially be three-state. if it is necessary to have the desired polarity on the pin at power-up in this configuration, attach a schottky diode between the run pin of the propagated power good signal and the gpio pin. the cathode must be attached to run and the anode to the gpio pin (see figure 2). if the gpio pin is set to a power good status, the mfr_gpio_response must be ignore otherwise a latched off condition exists. as described in the soft-start section, it is possible to control start-up through concatenated events. if gpion is used to drive the run pin of another controller, the unfiltered vout_uv fault limit should be mapped to the gpio pin. any fault or warning event will cause the alert pin to assert low unless the alert is masked by the smbalert_ mask command . the pin will remain asserted low until the clear_ faults command is issued, the fault bit is written to a 1, the pmbus master successfully reads the device ara register, bias power is cycled or a mfr_ reset or restore _ user_ all command is issued . channel specific faults are cleared if the run pins are toggled off/ on or the part is commanded off/ on via pmbus. if bit 0 of mfr_ config_ all is set to a 1, toggling the run pins off/ on or commanding the part off/ on via pmbus clears all faults. the mfr_ gpio_ propagate n command determines if the gpio pins are pulled low when a fault is detected; however, the alert pin is always pulled low if a fault or warning is detected and the status bits are updated unless the alert pin is masked using the smbalert_ mask command. output and input fault event handling is controlled by the corresponding fault response byte as specified in table 24 to table 28. shutdown recovery from these types of faults can either be autonomous or latched. for autonomous recovery, the faults are not latched, so if the fault condition is not present after the retry interval has elapsed , a new soft- start is attempted. if the fault persists, the controller will continue to retry. the retry interval is specified by the mfr_ retry_ delay command and prevents damage to the regulator components by repetitive power cycling. the mfr_ retry_ delay must be greater than 120ms. it can not exceed 83.88 seconds. channel - to - channel fault dependencies can be created by connecting gpio n pins together. in the event of an internal fault, one or more of the channels is configured to pull the bussed gpio n pins low. the other channels are then configured to shut down when the gpio n pins are pulled low. for autonomous group retry, the faulted channel is configured to release the gpio n pin( s ) after a retry interval, assuming the original fault has cleared. all the channels in the group then begin a soft- start sequence. if the fault response is latch_ off, the gpio pin remains asserted low until either the run pin is toggled off/ on or the part is commanded off/ on. the toggling of the run either by the pin or off/ on command will clear faults associated with the channel. if it is desired to have ltm 4675 4675f
35 for more information www.linear.com/ltm4675 operation all faults cleared when either run pin is toggled, set bit 0 of mfr_ config_ all to a 1. the status of all faults and warnings is summarized in the status_word and status_ byte commands. responses to v out and i out faults v out ov and uv conditions are monitored by comparators . the ov and uv limits are set in three ways. n as a percentage of the v out if using the resistor con- figuration pins n in eeprom if either programmed at the factory or through the gui n by pmbus command the i in and i out overcurrent monitors are performed by adc readings and calculations. thus these values are based on average currents and can have a nominal time latency of up to 100ms. the i out calculation accounts for the power inductor dcr and the temperature coefficient of the inductor ' s copper winding . the input current is equal to the sum of output current times the respective channel duty cycle plus the input offset current for each channel. if this calculated input current exceeds the iin _ oc _ warn _ limit the alert pin is pulled low and the iin_oc_warn bit is asserted in the status_input register. the ltm4675 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). the retry interval is set in mfr_retry_ delay n and can be from 120ms to 83.88 seconds in 1ms incre- ments. the shutdown for ov/uv and oc can be done immediately or after a user selectable deglitch time. output overvoltage fault response a programmable overvoltage comparator (ov) guards against transient overshoots as well as long-term over- voltages at the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared regardless of the pmbus vout _ ov_ fault _ response n command byte value . this hardware level fault response delay is typically 2s from the overvoltage condition to bg asserted high. using the vout_ov_fault_response n command, the user can select any of the following behaviors: n ov pull-down only (ov cannot be ignored) n shut down (stop switching) immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_ delay n either the latch off or retry fault responses can be de- glitched in increments of (0 to 7) ? 10s. see table 24. output undervoltage response the response to an undervoltage comparator output can be either: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_ delay n either the latch off or retry fault responses can be de- glitched in increments of (0 to 7) ? 10s. see table 25. peak output overcurrent fault response due to the current mode control algorithm, peak inductor current is always limited on a cycle by cycle basis. the value of the peak current limit is specified in the electrical characteristics table. the current limit circuit operates by limiting the comp n a maximum voltage. dcr sensing is used so the comp n a maximum voltage has a temperature dependency directly proportional to the tc of the dcr of the inductor. the ltm4675 automatically monitors the power stage temperature sensors and modifies the maximum allowed comp n a to compensate for this term. the overcurrent fault processing circuitry can execute the following behaviors: n current limit indefinitely n shut down immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_ delay n the overcurrent responses can be deglitched in increments of (0 to 7) ? 16ms. see table 26. ltm 4675 4675f
36 for more information www.linear.com/ltm4675 operation responses to timing faults ton_max_fault_limit n is the time allowed for v out to rise and settle at start-up. the ton_max_fault_limit n condition is predicated upon detection of the vout_uv_ fault _ limit n as the output is undergoing a soft _ start sequence. the ton_max_fault_limit n time is started after ton_delay n has been reached and a soft_ start sequence is started. the resolution of the ton_max_ fault_limit n is 10s. if the vout_uv_fault_limit n is not reached within the ton_max_fault_limit n time, the response of this fault is determined by the value of the ton _ max _ fault _ response n command value . this response may be one of the following: n ignore n shut down (stop switching) immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_ delay n this fault response is not deglitched. a value of 0 in ton _max _fault _limit n means the fault is ignored . the ton_max_fault_limit n should be set longer than the ton_rise n time. it is recommended ton_max_fault_ limit n always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user. see table 28. responses to sv in ov faults sv in overvoltage is measured with the adc; therefore, the response is naturally deglitched by up to the 100ms typical response time of the adc. the fault responses are: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_ delay n see table 28. responses to ot/ut faults internal overtemperature fault/ warn response an internal temperature sensor protects against eeprom damage. above 85c, no writes to eeprom are recom- mended. above 130c, the internal over temperature warn threshold is exceeded and the part disables eeprom writes and does not re-enable until the temperature has dropped to 125c. when the die temperature exceed 160c the internal over temperature fault response is enabled and the pwm is disabled until the die temperature drops below 150c. temperature is measured by the adc. internal temperature faults cannot be ignored . internal temperature limits cannot be adjusted by the user. see table 27. external overtemperature and undertemperature fault response two temperature sensors within the ltm4675 are used to sense power stage temperature . the ot _ fault _ response n and ut_fault_response n commands are used to determine the appropriate response to an over - temperature and undertemperature condition , respectively . the fault responses are: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_ delay n see table 28. responses to external faults when either gpio n pin is pulled low, the other bit is set in the status _ word command , the appropriate bit is set in the status_mfr_specifc command, and the alert pin is pulled low. responses are not deglitched. each channel can be configured to ignore or shut down then retry in response to its gpio n pin going low by modifying the mfr _ gpio _ response n command . to avoid the alert pin asserting low when gpio is pulled low, assert bit 1 of mfr_chan_config n , or mask the alert using the smbalert_mask command. ltm 4675 4675f
37 for more information www.linear.com/ltm4675 fault logging the ltm4675 has fault logging capability. data is logged into memory in the order shown in table 30. the data to be stored in the fault log is being continuously stored in internal volatile memory. when a fault event occurs, the recording into internal volatile memory is halted, the fault log information is available from the mfr_fault_log command , and the contents of the internal memory are copied into eeprom. fault logging is allowed at temperatures above 85c ; however, retention of 10 years is not guaranteed. when the die temperature exceeds 130c the fault logging is delayed until the die temperature drops below 125c. after the fault condition that created the fault log event has been removed, clear the fault before the fault log data is erased, or else the part will immediately issue another fault log. when the ltm4675 powers-up, it checks the eeprom for a valid fault log. if a valid fault log exists in eeprom , the valid fault log bit in the status_mfr_specific command will be set and an alert event will be generated . also, fault logging will be blocked until the ltm4675 has received a mfr_fault_log_clear command before fault logging will be re-enabled. the information is stored in eeprom in the event of any fault that disables the controller on either channel. an external gpio n pulling low will not trigger a fault logging event. operation bus timeout protection the ltm4675 implements a timeout feature to avoid hanging the serial interface. the data packet timer begins at the first start event before the device address write byte. data packet information must be completed within 25ms or the ltm4675 will three-state the bus and ignore the given data packet. if more time is required, assert bit 3 of mfr_config_all to allow typical bus timeouts of 255ms. data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the pec byte if applicable. the ltm4675 allows longer pmbus timeouts for block read data packets. this timeout is proportional to the length of the block read. the additional block read timeout applies primarily to the mfr_fault_log command. in no circumstances will the timeout period be less than the t timeout_smb specification of 32ms (typical). the user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface . the ltm4675 supports the full pmbus frequency range from 10khz to 400khz. ltm 4675 4675f
38 for more information www.linear.com/ltm4675 pmbus command summary pmbus commands table 1 lists supported pmbus commands and manufacturer specific commands. a complete description of these commands can be found in the pmbus power system management protocol specification C part ii C revision 1.2." users are encouraged to reference this specification. exceptions or manufacturer specific implementations are listed in table 1. all commands from 0xd0 through 0xff not listed in this table are implicitly reserved by the manufacturer. users should avoid blind writes within this range of commands to avoid undesired operation of the part. all commands from 0 x 00 through 0 xcf not listed in this table are implicitly not supported by the manufacturer. attempting to access non- supported or reserved commands may result in a cml command fault event. all output voltage settings and measurements are based on the vout_mode setting of 0 x14. this translates to an exponent of 2C12. if pmbus commands are received faster than they are being processed, the part may become too busy to handle new commands. in these circumstances the part follows the protocols defined in the pmbus specification v1.2, part ii, section 10.8.7, to communicate that it is busy. the part includes handshaking features to eliminate busy errors and simplify error handling software while ensuring robust communication and system behavior. please refer to the pmbus communication and command processing subsection in the applications information section for details. table 1. summary of supported commands pmbus command name, or feature cmd code ( register ) command or feature description ltm4675 nvm factory- default value and/or attributes page page 0x00 channel or page currently targeted for paged communications. 0x00, read/write, non-paged, not stored in nvm. 82 operation n 0x01 operating mode control. on/off, margin high and margin low. 0x80, read/write, paged, stored in user-editable nvm. 86 on _off_config n 0x02 run n pin and on/off configuration. 0x1f, read/write, paged, stored in user-editable nvm. 85 clear_ faults 0x03 clear any fault bits that have been set. default value not applicable, send byte only, non-paged, not stored in nvm. 109 page_plus_write 0x05 write a command directly to a specified page. default value not applicable, write-only, non-paged, not stored in nvm. 82 page_plus_read 0x06 read a command directly from a specified page. default value not applicable, read/write, non-paged, not stored in nvm. 83 write_protect 0x10 level of protection provided by the device against accidental changes. 0x00, read/write, non-paged, stored in user-editable nvm. 83 store_user_all 0x15 store user operating memory to eeprom (user-editable nvm). default value not applicable, send byte only, non-paged, not stored in nvm. 120 restore_user_ all 0x16 restore user operating memory from eeprom. default value not applicable, send byte only, non- paged, not stored in nvm. identical to mfr_ reset command (0xfd). 120 capability 0x19 summary of pmbus optional communication protocols supported by this device. 0xb0, read-only, non-paged, not stored in nvm. 108 smbalert_mask n 0x1 b mask alert activity. default mask values: status_vout n =0x00, status_iout n =0x00, status_input=0x00, status_temperature n = 0x00, status_ cml=0x00, status_mfr_specific n =0x11. read/write, paged as indicated, 10 bytes total, stored in nvm 110 vout_mode n 0x20 output voltage format/exponent. 0x14 (2 C12 ), read-only, paged, not stored in nvm. 90 vout_command n 0x21 nominal output voltage set point. 0x1000 (1.000v), read/write, paged, stored in user-editable nvm. 91 ltm 4675 4675f
39 for more information www.linear.com/ltm4675 pmbus command summary table 1. summary of supported commands pmbus command name, or feature cmd code ( register ) command or feature description ltm4675 nvm factory- default value and/or attributes page vout_max n 0x24 the upper limit on the commandable output voltage. page 0x00: 0x599a (5.600v) page 0x01: 0x599a (5.600v) read/write, paged, stored in user-editable nvm. 90 vout_margin_ high n 0x25 margin high output voltage set point. must be greater than vout_command n . 0x10cd (1.050v), read/write, paged, stored in user-editable nvm. 91 vout_margin_ low n 0x26 margin low output voltage set point. must be less than vout_command n . 0x0f33 (0.950v), read/write, paged, stored in user-editable nvm. 92 vout_transition_ rate n 0x27 the rate at which the output voltage changes when vout n is commanded to a new value via i 2 c. 0x8042 (0.001v/ms), read/write, paged, stored in user-editable nvm. 97 frequency_ switch 0x33 the switching frequency setting. 0xfbe8 (500khz), read/write, non-paged, stored in user-editable nvm. 89 vin_on 0x35 the undervoltage lockout (uvlo)- rising threshold. 0xcac0 (5.500v), as monitored on the sv in pin, read/write, non-paged, stored in user-editable nvm. 90 vin_off 0x36 the undervoltage lockout (uvlo)- falling threshold. 0xcaa0 (5.250v) , as monitored on the sv in pin, read/write, non-paged, stored in user-editable nvm. 90 iout_cal_gain n 0x38 the ratio of the voltage at the control ics current-sense pins to the sensed current, in m, at 25c. trimmed at ate , read/write, paged, stored in factory-only nvm. writes to this register not recommended. 93 vout _ov_fault_ limit n 0x40 output overvoltage fault limit. 0x119a (1.100v), read/write, paged, stored in user-editable nvm. 91 vout_ov_fault_ response n 0x41 action to be taken by the device when an output overvoltage fault is detected. 0x7a (20s glitch filter; non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. 100 vout_ov_warn_ limit n 0 x42 output overvoltage warning threshold. 0x1133 (1.075v), read/write, paged, stored in user-editable nvm. 91 vout_uv_warn_ limit n 0x43 output undervoltage warning threshold. 0x0ecd (0.925v), read/write, paged, stored in user-editable nvm. 92 vout_uv_fault_ limit n 0x44 output undervoltage fault limit. 0x0e66 (0.900v), read/write, paged, stored in user-editable nvm. 92 vout_uv_fault_ response n 0x45 action to be taken by the device when an output undervoltage fault is detected. 0xb8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. 101 iout_oc_fault_ limit n 0x46 output overcurrent fault threshold (cycle-by-cycle inductor peak current). 0xd3f3 (15.80a), read/write, paged, stored in user-editable nvm. 94 iout_oc_fault_ response n 0x47 action to be taken by the device when an output overcurrent fault is detected. 0x00 (try to regulate through the fault condition/event; limit the cycle-by- cycle peak of the inductor current to not exceed the commanded iout_ oc_fault_limit), read/write, paged, stored in user-editable nvm. 103 iout_oc_warn_ limit n 0x4a output overcurrent warning threshold (time-averaged inductor current). 0xd2b3 (10.80a), read/write, paged , stored in user-editable nvm. 95 ot_fault_limit n 0x4f overtemperature fault threshold. 0xf200 (128c), read/write, paged, stored in user-editable nvm. 96 ltm 4675 4675f
40 for more information www.linear.com/ltm4675 pmbus command summary table 1. summary of supported commands pmbus command name, or feature cmd code ( register ) command or feature description ltm4675 nvm factory- default value and/or attributes page ot_fault_ response n 0x50 action to be taken by the device when an overtemperature fault is detected via tsns n a . 0xb8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. 105 ot_warn_limit n 0x51 overtemperature warning threshold. 0xebe8 (125c), read/write, paged, stored in user-editable nvm. 96 ut_fault_limit n 0x53 undertemperature fault threshold. 0xe530 (C45c), read/write, paged, stored in user-editable nvm. 96 ut_fault_ response n 0x54 response to undertemperature fault events. 0x00 (ignore; continue without interruption), read/write, paged, stored in user-editable nvm, read/write, paged, stored in user-editable nvm. 105 vin_ov_fault_ limit 0x55 input supply (sv in ) overvoltage fault limit. 0xda2e (17.44v), read/write, non-paged, stored in user-editable nvm. 89 vin_ov_fault_ response n 0x56 response to input overvoltage fault events. 0xb8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. 99 vin_uv_warn_ limit 0x58 input undervoltage warning threshold. 0xcaa6 (5.297v), read/write, non-paged, stored in user-editable nvm. 89 iin_oc_warn_ limit 0x5d input supply overcurrent warning threshold. 0xd220 (8.5a), read/write, non-paged, stored in user-editable nvm. 93 ton_ delay n 0x60 time from run n and/or operation n on to output rail turn-on. 0x8000 (0ms), read/write, paged, stored in user-editable nvm. 97 ton_rise n 0x61 time from when the output voltage reference starts to rise until it reaches its commanded setting. 0xc300 (3ms), read/write, paged, stored in user-editable nvm. 97 ton_max_fault_ limit n 0x62 turn-on watchdog timeout fault threshold (time permitted for vout n to reach or exceed vout_ uv_fault_limit n after turn-on command is received). 0xca80 (5ms), read/write, paged, stored in user-editable nvm. 97 ton_max_fault_ response n 0x63 action to be taken by the device when a ton_max_ fault n event is detected. 0xb8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. 102 toff_ delay n 0x64 time from run and/or operation off to the start of toff_ fall n ramp. 0x8000 (0ms), read/write, paged, stored in user-editable nvm. 98 toff_ fall n 0x65 time from when the output voltage reference starts to fall until it reaches 0v. 0xc300 (3ms), read/write, paged, stored in user-editable nvm. 98 toff_max_warn_ limit n 0x66 turn -off watchdog timeout fault threshold (time permitted for vout n to decay to or below 12.5% of the commanded vout n value at the time of receiving a turn-off command). 0x8000 (no limit; warning is disabled), read/write, paged, stored in user- editable nvm. 98 status_ byte n 0x78 one byte summary of the units fault condition. default value not applicable, read/write, paged, not stored in nvm. 111 status_word n 0x79 tw o byte summary of the units fault condition. default value not applicable, read/write, paged, not stored in nvm. 111 ltm 4675 4675f
41 for more information www.linear.com/ltm4675 pmbus command summary table 1. summary of supported commands pmbus command name, or feature cmd code ( register ) command or feature description ltm4675 nvm factory- default value and/or attributes page status_vout n 0x7a output voltage fault and warning status. default value not applicable, read/write, paged, not stored in nvm. 112 status_iout n 0x7b output current fault and warning status. default value not applicable, read/write, paged, not stored in nvm. 112 status_input 0x7c input supply (sv in ) fault and warning status. default value not applicable, read/write, non-paged, not stored in nvm. 112 status_ temperature n 0x7d tsns n a -sensed temperature fault and warning status for read_ temerature_1 n . default value not applicable, read/write, paged, not stored in nvm. 113 status_cml 0x7e communication and memory fault and warning status. default value not applicable, read/ write, non-paged, not stored in nvm. 113 status_mfr_ specific n 0x80 manufacturer specific fault and state information. default value not applicable, read/write, paged, not stored in nvm. 113 read_vin 0x88 measured input supply (sv in ) voltage. default value not applicable, read-only, non-paged, not stored in nvm. 116 read_iin 0x89 calculated total input supply current. default value not applicable, read-only, non-paged, not stored in nvm. 116 read_vout n 0x8b measured output voltage. default value not applicable, read-only, paged, not stored in nvm. 116 read_iout n 0x8c measured output current. default value not applicable, read-only, paged, not stored in nvm. 117 read_ temperature_1 n 0x8d measurement of tsns n a - sensed temperature. default value not applicable, read-only, paged, not stored in nvm. 117 read_ temperature_2 0x 8e measured control ic junction temperature. default value not applicable, read-only, non-paged, not stored in nvm. 117 read_duty_ cycle n 0x94 measured duty cycle of mt n . default value not applicable, read-only, paged, not stored in nvm. 117 read_pout n 0x96 calculated output power. default value not applicable, read-only, paged, not stored in nvm. 117 pmbus_revision 0x98 pmbus revision supported by this device. 0x22 (revision 1.2 of part i and revision 1.2 of part ii of pmbus specification documents), read-only, non-paged, not stored in nvm. 108 mfr_id 0x99 manufacturer identification, in ascii lt c , read-only, non-paged. 108 mfr_model 0x9a manufacturers part number, in ascii ltm4675, read-only, non-paged. 109 mfr_serial 0x9e serial number of this specific unit. up to nine bytes of custom-formatted data that identify the units configuration, read-only, non-paged. 109 mfr_vout_max n 0xa5 maximum allowed output voltage. 0x5b34 (5.700v) on both channels. read-only, paged, not stored in user- editable nvm. 92 user_data_00 0xb0 oem reserved data. read/write, non-paged, stored in user-editable nvm. recommended against altering. 108 user_data_01 n 0xb1 oem reserved data. read/write, paged, stored in user-editable nvm. recommended against altering. 108 user_data_02 0xb2 oem reserved data. read/write, non-paged, stored in user-editable nvm. recommended against altering. 108 user_data_03 n 0xb3 user-editable words available for the user. 0x0000, read/write, paged, stored in user-editable nvm. 108 user_data_04 0xb4 a user-editable word available for the user. 0x0000, read/write, non-paged, stored in user-editable nvm. 108 ltm 4675 4675f
42 for more information www.linear.com/ltm4675 table 1. summary of supported commands pmbus command name, or feature cmd code ( register ) command or feature description ltm4675 nvm factory- default value and/or attributes page mfr_ee_unlock 0xbd unlock user eeprom for access by mfr_ee_erase and mfr_ee_ data commands. default value not applicable, read/write, non-paged, not stored in nvm. 124 mfr_ee_erase 0xbe initialize user eeprom for bulk programming by mfr_ee_ data . default value not applicable, read/write, non-paged, not stored in nvm. 124 mfr_ee_ data 0xbf data transferred to and from eeprom using sequential pmbus word reads or writes. supports bulk programming. default value not applicable, read/write, non-paged, not stored in nvm. 124 mfr_chan_ config_* n 0xd0 channel-specific configuration bits. 0x1f, read/write, paged, stored in user-editable nvm. register is named mfr_chan_config and referred to as mfr_chan_config_ ltm467x in ltpowerplay. 84 mfr _ config _ all _ * 0xd1 global configuration bits, i.e., common to both v out channels 0 and 1. 0x09, read/write, non-paged, stored in user-editable nvm. bit 4 configures whether the sync drive circuit is active (0 b ) or inactive (1 b ); bit 3 configures whether the stuck pmbus timer timeout is 150ms for block reads and 32ms for non-block reads (0 b ) or 250ms for all reads (1 b ). register is named "mfr_config_all_ltm467x in ltpowerplay. 85 mfr_gpio_ propagate_* n 0xd2 configuration bits for propagating faults to the gpio n pins. 0x6893, read/write, paged, stored in user-editable nvm. register is named mfr_gpio_propagate and referred to as mfr_gpio_ propagate_ltm467x in ltpowerplay . 106 mfr_pwm_ mode_* n 0xd4 configuration for the pwm engine of each v out channel. 0xc1, read/write, paged, stored in user-editable nvm. bit 1 commands whether the output is in high range (0 b ) or low range (1 b ). bit 0 commands whether the output is operating in forced continuous conduction mode (1 b ) or discontinuous mode (0 b ). command is named mfr_pwm_mode and referred to as mfr_pwm_ mode_ltm467x in ltpowerplay. 87 mfr_gpio_ response n 0xd5 action to be taken by the device when the gpio n pin is asserted low by circuitry external to the unit. 0xc0 (make the respective outputs power stage high impedance, i.e., three-stated; autonomous restart upon fault removal), read/write, paged, stored in user-editable nvm. 107 mfr_ot_fault_ response 0xd6 action to be taken by the device when a control ic junction overtemperature fault is detected. 0xc0 (make the respective outputs power stage high impedance, i.e., three-stated; autonomous restart upon fault removal), read-only, non- paged, not stored in user-editable nvm. 104 mfr_iout_peak n 0xd7 maximum measured value of read_iout n since the last mfr_ clear_peaks. default value not applicable, read- only, paged, not stored in nvm. 118 mfr_adc_ control 0xd8 adc telemetry parameter for repeated fast adc readback. 0x00, read/write, not paged, not stored in nvm. allows telemetry readback rates up to 125hz instead of 10hz, nominal. 118 mfr_adc_ telemetry_ status 0xda adc status during short-loop. default value not applicable, read/write, not paged, not stored in nvm. adc status indicating most recently digitized telemetry when engaged in short round-robin loop (mfr_adc_control=0x0d) 119 mfr_retry_ delay n 0xdb retry interval during fault- retry mode. 0xf3e8 (250ms), read/write, paged, stored in user-editable nvm. 99 mfr_restart_ delay n 0xdc minimum interval (nominal) the run n pin is pulled logic low by internal circuitry. 0xf258 (150ms), read/write, paged, stored in user-editable nvm. 99 pmbus command summary ltm 4675 4675f
43 for more information www.linear.com/ltm4675 pmbus command summary table 1. summary of supported commands pmbus command name, or feature cmd code ( register ) command or feature description ltm4675 nvm factory- default value and/or attributes page mfr_vout_peak n 0xdd maximum measured value of read_vout n since the last mfr_clear_peaks. default value not applicable, read-only, paged, not stored in nvm. 117 mfr_vin_peak 0xde maximum measured value of read_vin since the last mfr_ clear_peaks . default value not applicable, read-only, non-paged, not stored in nvm. 118 mfr_ temperature_1_ peak n 0xdf maximum value of tsns na measured temperature since the last mfr_clear_peaks. default value not applicable, read-only, paged, not stored in nvm. 118 mfr_clear_peaks 0xe3 clears all peak values. default value not applicable, send byte only, non-paged, not stored in nvm. 110 mfr_ pads 0xe5 digital status of the i/o pads. default value not applicable, read-only, non-paged, not stored in nvm. 114 mfr_address 0xe6 ltm4675's i 2 c slave address, right-justified. 0x4f, read/write, non-paged, stored in user-editable nvm. bits[6:4] represent the user-configurable upper 3 bits of the 7-bit slave address of the device. bits[3:0] are dictated by the asel resistor pin-strap setting. setting this command to 0x80 disables device-specific addressing. 84 mfr_special_id 0xe7 manufacturer code representing ic silicon and revision 0x47ax, read-only, non-paged. 109 mfr_iin_offset n 0xe9 coefficient used in calculations of read_iin and mfr_read_iin n , representing the contribution of input current drawn by the control ic, including the mosfet drivers. 0x8bc9 (0.02956a), read/write, paged, stored in user- editable nvm. 93 mfr_fault_log_ store 0xea commands a transfer of the fault log from ram to eeprom. this causes the part to behave as if a channel has faulted off. default value not applicable, send byte only, non-paged, not stored in nvm. 121 mfr_fault_log_ clear 0xec initialize the eeprom block reserved for fault logging and clear any previous fault logging locks. default value not applicable, send byte only, non-paged, not stored in nvm. 124 mfr_read_iin n 0xed calculated input current, by channel. default value not applicable, read-only, paged, not stored in nvm. 117 mfr_fault_log 0xee fault log data bytes. this sequentially retrieved data is used to assemble a complete fault log. default value not applicable, read-only, non-paged, stored in fault-log nvm. 120 mfr_common 0xef manufacturer status bits that are common across multiple lt c ics/ modules. default value not applicable, read-only, non-paged, not stored in nvm. 114 mfr_compare_ user_all 0xf0 compares current command contents (ram) with nvm. default value not applicable, send byte only, non-paged, not stored in nvm. 120 mfr_ temperature_2_ peak 0xf4 maximum measured control ic junction temperature since last mfr_clear_peaks. default value not applicable , read-only, non-paged, not stored in nvm. 118 ltm 4675 4675f
44 for more information www.linear.com/ltm4675 table 1. summary of supported commands pmbus command name, or feature cmd code ( register ) command or feature description ltm4675 nvm factory- default value and/or attributes page mfr_pwm_ config_* 0xf5 configuration bits for setting the phase interleaving angles of channels 0 and 1, share_clk behavior in uvlo, and using the fully differential amplifier to regulate paralleled output channels. 0x10, read/write, non-paged, stored in user-editable nvm. when bit 7 is 0 b , channel 1's output is regulated by the v osns1 and sgnd feedback signals. when bit 7 is 1 b , channel 1's output is regulated by the v osns0 + and v osns0 C feedback signals. only set bit 7 to 1 b for polyphase rail applications. the command is named mfr_pwm_config and referred to as mfr_pwm_config_ltm467x in ltpowerplay. 88 mfr_iout_cal_ gain_tc n 0xf6 temperature coefficient of the current sensing element. 0x0f14 (3860ppm/c), read/write, paged, stored in user-editable nvm. 93 mfr_temp_1_ gain n 0xf8 sets the slope of the temperature sensors that interface to tsns na . 0x3 fae (0.995, in custom units), read/write, paged, stored in user- editable nvm. 95 mfr_temp_1_ offset n 0xf9 sets the offset of the tsns na temperature sensor with respect to C273.1c. 0x8000 (0.0), read/write, paged, stored in nvm. 95 mfr_rail_ address n 0 xfa common address for polyphase outputs to adjust common parameters. 0x80, read/write, paged, stored in nvm. 84 mfr_reset 0xfd commanded reset without requiring a power down. default value not applicable, send byte only, non-paged, not stored in nvm. identical to restore_user_all. 87 pmbus command summary ltm 4675 4675f
45 for more information www.linear.com/ltm4675 applications information table 2. v outn cfg pin strapping look-up table for the ltm4675's output voltage, coarse setting (not applicable if mfr_config_all[6] = 1 b ) r voutn cfg * (k) v outn (v) setting coarse mfr_pwm_mode n [1] bit open nvm nvm 32.4 see table 3 see table 3 22.6 3.3 0 18.0 3.1 0 15.4 2.9 0 12.7 2.7 0 10.7 2.5 0, if v trimn > 0mv 1, if v trimn 0mv 9.09 2.3 1 7.68 2.1 1 6.34 1.9 1 5.23 1.7 1 4.22 1.5 1 3.24 1.3 1 2.43 1.1 1 1.65 0.9 1 0.787 0.7 1 0 0.5 1 *r voutn cfg value indicated is nominal. select r voutn cfg from a resistor vendor such that its value is always within 3% of the value indicated in the table. take into account resistor initial tolerance, t.c.r. and resistor operating temperatures, soldering heat/ir reflow, and endurance of the resistor over its lifetime. thermal shock/cycling, moisture (humidity) and other effects (depending on ones specific application) could also affect r voutn cfg s value over time. all such effects must be taken into account in order for resistor pin strapping to yield the expected result at every sv in power-up and/or every execution of mfr_reset or restore_ user_all, over the lifetime of ones product. table 3. v trimn cfg pin strapping look-up table for the ltm4675's output voltage, fine adjustment setting (not applicable if mfr_config_all[6] = 1 b ) r vtrim n cfg * (k) v trim (mv) fine adjustment to v outn setting when respective r voutn cfg 32.4k v outn output voltage setting (v) when v outn cfg pin uses r cfg = 32.4k mfr_pwm_ mode n [1] bit open 0 nvm 0, if vout _ov_ fault_limit n > 2.75v 1, if vout_ov_ fault_limit n 2.75v 32.4 99 22.6 86.625 18.0 74.25 15.4 61.875 12.7 49.5 10.7 37.125 5.50 0 9.09 24.75 5.25 0 7.68 12.375 5.00 0 6.34 C12.375 4.75 0 5.23 C24.75 4.50 0 4.22 C37.125 4.25 0 3.24 C49.5 4.00 0 2.43 C61.875 3.75 0 1.65 C74.25 3.63 0 0.787 C86.625 3.50 0 0 C99 3.46 0 *r vtrimn cfg value indicated is nominal. select r vtrimn cfg from a resistor vendor such that its value is always within 3% of the value indicated in the table. take into account resistor initial tolerance, t.c.r. and resistor operating temperatures, soldering heat/ir reflow, and endurance of the resistor over its lifetime. thermal shock/cycling, moisture (humidity) and other effects (depending on ones specific application) could also affect r vtrimn cfg s value over time. all such effects must be taken into account in order for resistor pin strapping to yield the expected result at every sv in power-up and/or every execution of mfr_reset or restore_user_all, over the lifetime of ones product. ltm 4675 4675f
46 for more information www.linear.com/ltm4675 applications information table 4. f swphcfg pin strapping look- up table to set the ltm4675' s switching frequency and channel phase- interleaving angle (not applicable if mfr_config_all[6] = 1 b ) r fswphcfg * (k) switching frequency (khz) sync to 0 sync to 1 bits [2:0] of mfr_pwm_config bit [4] of mfr_config_all open nvm; ltm4675 default = 500 nvm; ltm4675 default = 0 nvm; ltm4675 default = 180 nvm; ltm4675 default = 000 b nvm; ltm 4675 default = 0 b 32.4 250 0 180 000 b 0 b 22.6 350 0 180 000 b 0 b 18.0 425 0 180 000 b 0 b 15.4 575 0 180 000 b 0 b 12.7 650 0 180 000 b 0 b 10.7 750 0 180 000 b 0 b 9.09 1000 0 180 000 b 0 b 7.68 500 120 240 100 b 0 b 6.34 500 90 270 001 b 0 b 5.23 external** 0 240 010 b 1 b 4.22 external** 0 120 011 b 1 b 3.24 external** 60 240 101 b 1 b 2.43 external** 120 300 110 b 1 b 1.65 external** 90 270 001 b 1 b 0.787 external** 0 180 000 b 1 b 0 external** 120 240 100 b 1 b *r fswphcfg value indicated is nominal. select r fswphcfg from a resistor vendor such that its value is always within 3% of the value indicated in the table. take into account resistor initial tolerance, t.c.r. and resistor operating temperatures, soldering heat/ir reflow, and endurance of the resistor over its lifetime. thermal shock/cycling, moisture (humidity) and other effects (depending on ones specific application) could also affect r fswphcfg s value over time. all such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every sv in power-up and/or every execution of mfr_reset or restore_user_all, over the lifetime of ones product. **"external" setting corresponds to the frequency_switch (command 0x33) value set to 0x0000; the device synchronizes its switching frequency to that of the clock provided on the sync pin, provided mfr_config_all[4]=1 b . ltm 4675 4675f
47 for more information www.linear.com/ltm4675 applications information table 5. asel pin strapping look-up table to set the ltm4675's slave address (applicable regardless of mfr_config_all[6] setting) r asel * (k) slave address open 100_1111_r/w 32.4 100_1111_r/w 22.6 100_1110_r/w 18.0 100_1101_r/w 15.4 100_1100_r/w 12.7 100_1011_r/w 10.7 100_1010_r/w 9.09 100_1001_r/w 7.68 100_1000_r/w 6.34 100_0111_r/w 5.23 100_0110_r/w 4.22 100_0101_r/w 3.24 100_0100_r/w 2.43 100_0011_r/w 1.65 100_0010_r/w 0.787 100_0001_r/w 0 100_0000_ r/w where: r/w = read/write bit in control byte. all pmbus device addresses listed in the specification are 7 bits wide unless otherwise noted. note: the ltm4675 will always respond to slave address 0x5a and 0x5b regardless of the nvm or asel resistor configuration values. *r cfg value indicated is nominal. select r cfg from a resistor vendor such that its value is always within 3% of the value indicated in the table. take into account resistor initial tolerance, t.c.r. and resistor operating temperatures, soldering heat/ir reflow, and endurance of the resistor over its lifetime. thermal shock cycling, moisture (humidity) and other effects (depending on ones specific application) could also affect r cfg s value over time. all such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every sv in power-up and/or every execution of mfr_reset or restore_user_all, over the lifetime of ones product. table 6. ltm4675 mfr_address command examples expressed in 7- and 8-bit addressing description hex device address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 7 bit 8 bit rail 4 0x5a 0xb4 0 1 0 1 1 0 1 0 0 global 4 0x5b 0xb6 0 1 0 1 1 0 1 1 0 default 0x4f 0x9e 0 1 0 0 1 1 1 1 0 example 1 0x40 0x80 0 1 0 0 0 0 0 0 0 example 2 0x 41 0x82 0 1 0 0 0 0 0 1 0 disabled 2,3 1 0 0 0 0 0 0 0 0 note 1: this table can be applied to the mfr_rail_address n command, but not the mfr_address command. note 2: a disabled value in one command does not disable the device, nor does it disable the global address. note 3: a disabled value in one command does not inhibit the device from responding to device addresses specified in other commands. note 4: it is not recommended to write the value 0x00, 0x0c (7 bit), 0x5a (7 bit), 0x5b (7 bit), or 0x7c (7 bit) to the mfr_rail_ address n or mfr_address commands. ltm 4675 4675f
48 for more information www.linear.com/ltm4675 applications information v in to v out step-down ratios there are restrictions in the maximum v in and v out step- down ratio that can be achieved for a given input voltage. each output of the ltm4675 is capable of 95% duty cycle at 500khz, but the v in to v out minimum dropout is still a function of its load current and will limit output current capability related to high duty cycle on the topside switch. minimum on-time t on(min) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that t on(min) < d/f sw , where d is duty cycle and f sw is the switching frequency. t on(min) is specified in the electrical parameters as 90ns. see note 6 in the electrical characteristics section for output current guideline. input capacitors the ltm4675 module should be connected to a low ac- impedance dc source . for the regulator input four 22f input ceramic capacitors are used to handle the rms ripple current. a 47f to 100f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long in- ductive leads, traces or not enough source capacitance. if low impedance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty-cycle can be estimated as: d n = v out n v in n without considering the inductor current ripple, for each output, the rms current of the input capacitor can be estimated as: i cin n (rms) = i out n (max) % d n 1 ? d n ( ) in the above equation, k% is the estimated efficiency of the power module. the bulk capacitor can be a switcher-rated electrolytic aluminum capacitor, or a polymer capacitor. output capacitors the ltm4675 is designed for low output voltage ripple noise and good transient response . the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output volt- age ripple and transient requirements. c out can be a low esr tantalum capacitor, a low esr polymer capacitor or ceramic capacitor. the typical output capacitance range for each output is from 400f to 700f. additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is required. table 20 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 4.5a/s transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance . stability criteria are considered in the table 20 matrix , and the linear technology module power design tool will be provided for stability analysis. multiphase operation reduces effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. the linear technology module power design tool can calculate the output ripple reduc- tion as the number of implemented phases increases by n times. a small value 10? resistor can be placed in series from v outn to the v osns0 + or v osns 1 pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. light load current operation the ltm4675 has two modes of operation: high efficiency, discontinuous conduction mode or forced continuous conduction mode. the mode of operation is configured by bit 0 of the mfr_pwm_mode n command (discontinuous conduction is always the start - up mode , forced continuous is the default running mode). ltm 4675 4675f
49 for more information www.linear.com/ltm4675 applications information if a channel is enabled for discontinuous mode operation, the inductor current is not allowed to reverse. the reverse current comparator, i rev , turns off the bottom mosfet (mbn) just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller can operate in discontinuous (pulse-skippng) operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined solely by the voltage on the comp na pin. in this mode, the efficiency at light loads is lower than discontinuous mode operation . however , continuous mode exhibits lower output ripple and less interference with audio circuitry. forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. the vin_ov_fault_limit can detect this (if sv in is connected to v in0 and/or v in1 ) and turn off the offending channel. however, this fault is based on an adc read and can nominally take up to 100ms to detect. if there is a concern about the input supply boost- ing, keep the part in discontinuous conduction operation. switching frequency and phase the switching frequency of the ltm4675s channels is established by its analog phase - locked - loop ( pll ) locking on to the clock present at the modules sync pin. the clock waveform on the sync pin can be generated by the ltm4675s internal circuitry when an external pull-up resistor to 3.3v (e.g., v dd33 ) is provided, in combination with the ltm4675 control ics frequency_switch command being set to one of the following supported values : 250 khz , 350 khz , 425 khz , 500 khz , 575 khz , 650khz, 750khz, 1mhz (see table 8 for hexadecimal values). in this configuration, the module is called a sync master : using the factory - default setting of mfr _ config _ all [4]=0 b , sync becomes a bidirectional open-drain pin, and the ltm4675 pulls sync logic low for nominally 500ns at a time, at the prescribed clock rate. the sync signal can be bused to other ltm4675 modules (configured as sync slaves), for purposes of synchronizing switching frequencies of multiple modules within a systembut only one ltm4675 should be configured as a sync master; the other ltm4675(s) should be configured as sync slaves. there are two recommended ways to configure an ltm4675 as a sync slave: ? the most straightforward way is to set its frequency_ switch command to 0 x 0000 and mfr _ config _ all [4]=1 b . this can be easily implemented with resistor pin-strap settings on the f swphcfg pin (see table 4). using mfr_config_all[4]=1 b , the ltm4675s sync pin becomes a high impedance input, onlyi.e., it does not drive sync low. the module synchronizes its frequency to that of the clock applied to its sync pin. the only shortcoming of this approach is: in the absence of an externally applied clock, the switching frequency of the module will default to the low end of its frequency - synchronization capture range (~225 khz ). ? if fault - tolerance to the loss of an externally applied sync clock is desired, the frequency _ switch command of a sync slave can be left at the nominal target switching frequency of the application, and not 0x0000 (see table 7). however, it is then still necessary to configure mfr_config_all[4]=1 b . with this combination of configurations, the ltm4675s sync pin becomes a high impedance input and the module synchronizes its frequency to that of the externally applied clock, provided that the frequency of the externally applied clock exceeds ~? of the target frequency (frequency_switch). if the sync clock is absent, the module responds by op- erating at its target frequency, indefinitely. if and when the sync clock is restored, the module automatically phase-locks to the sync clock as normal. the only shortcoming of this approach is: the eeprom must be configured per above guidance; resistor pin-strapping options on the f swphcfg pin alone cannot provide fault-tolerance to the absence of the sync clock. the frequency_switch command can be altered via i 2 c commands, but only when switching action is disengaged, i.e., the modules outputs are turned off. the frequency _ switch command takes on the value stored in nvm at sv in power-up, but is overridden according to a resistor pin-strap applied between the f swphcfg pin and sgnd only if the module is configured to respect resistor pin-strap settings (mfr_config_all[6] = 0 b ). table 4 highlights available resistor pin - strap and corresponding frequency_switch settings. ltm 4675 4675f
50 for more information www.linear.com/ltm4675 applications information the relative phasing of all active channels in a polyphase rail should be optimally phased. the relative phasing of each rail is 360/n, where n is the number of phases in the rail. mfr_pwm_config[2:0] configures channel relative phasing with respect to the sync pin. phase relationship values are indicated with 0 corresponding to the falling edge of sync being coincident with the turn-on of the top mosfets, mtn. the mfr _ pwm _ config command can be altered via i 2 c commands, but only when switching action is disengaged, i.e., the modules outputs are turned off. the mfr_pwm_config command takes on the value stored in nvm at sv in power-up, but is overridden according to a resistor pin - strap applied between the f swphcfg pin and sgnd only if the module is configured to respect resistor pin-strap settings (mfr_config_all[6] = 0 b ). table 4 highlights available resistor pin-strap and corresponding mfr_pwm_config[2:0] settings. some combinations of frequency _ switch and mfr_pwm_config[2:0] are not available by resistor pin - strapping the f swphcfg pin . all combinations of supported values for frequency _ switch and mfr_pwm_config[2:0] can be configured by nvm programmingor, i 2 c transactions, provided switching action is disengaged, i.e., the modules outputs are turned off. care must be taken to minimize capacitance on sync to assure that the pull-up resistor versus the capacitor load has a low enough time constant for the application to form a clean clock. (see open-drain pins, later in this section.) when an ltm4675 is configured as a sync slave, it is permissible for external circuitry to drive the sync pin from a current-limited source (less than 10ma), rather than using a pull-up resistor. any external circuitry must not drive high with arbitrarily low impedance at sv in power - up , because the sync output can be low impedance until nvm contents have been downloaded to ram. recommended ltm4675 switching frequencies of operation for many common v in -to-v out applications are indicated in table 7. when the two channels of an ltm4675 are stepping input voltage(s) down to output voltages whose recommended switching frequencies in table 7 are significantly different, operation at the higher of the two recommended switching frequencies is preferable, but minimum on-time must be considered. (see minimum on-time considerations section.) for example, consider an application in which it is desired for an ltm4675 to step-down 12v in to 1v out on channel 0, and 12v in to 3.3v out on channel 1: according to table 7, the recommended switching frequency is 350khz and 650khz, respectively. however, the switching frequency setting of the ltm4675 is common to both channels. based on the aforementioned guidance, operation at 650khz would be preferredin order to keep inductor ripple currents reasonablehowever, it is then realized that the on- time for a 12v in - to-1v out condition at 650khz is only 128ns, which is marginal. therefore, for this particular example, the recommended switching frequency becomes 575khz. table 7. recommended switching frequency for various v in -to-v out step-down scenarios 5v in 8v in ~ 12v in 0.9v out 425khz 425khz 1.0v out 500khz 500khz 1.2v out 500khz 575khz 1.5v out 575khz 650khz 1.8v out 650khz 750khz 2.5v out 650khz 1mhz 3.3v out 650khz 1mhz 5.0v out n/a 1mhz the current drawn by the sv in pin of the ltm4675 is not digitized or computed. a value representing the estimated sv in current is located in the mfr _ iin _ offset n command , and is used in the computations of input current readback telemetry, namely read_iin and and mfr_read_iin n . the recommended setting of mfr _ iin _ offset n is found in table 8. the same value should be used for mfr_iin_offset 0 and mfr_iin_offset 1 (i.e., pages 0x00 and 0x01). ltm 4675 4675f
51 for more information www.linear.com/ltm4675 applications information minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ltm4675 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out n v in n f osc if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltm4675 is 90ns, nominal, guardband to 130ns. variable delay time, soft- start and output voltage ramping the ltm4675 must enter its run state prior to soft-start. the run n pins are released after the part initializes and sv in is greater than the vin_on threshold. if multiple ltm4675s are used in an application, they should be configured to share the same run n pins. they all hold their respective run n pins low until all devices initialize and sv in exceeds the vin_on threshold for all devices. the share_clk pin assures all the devices connected to the signal use the same time base. after the run n pin releases, the controller waits for the user - specified turn - on delay ( ton _ delay n ) prior to initiating an output voltage ramp. multiple ltm4675s and other ltc parts can be configured to start with variable delay times. to work correctly, all devices use the same timing clock ( share_clk) and all devices must share the run n pin. this allows the relative delay of all parts to be synchronized. the actual variation in the delay will be dependent on the highest clock rate of the devices connected to the share_clk pin (all linear technology ics are configured to allow the fastest share_clk signal to control the timing of all devices ). the share _ clk signal can be 7.5% in frequency, thus the actual time delays will have some variance. soft - start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0 v to the commanded voltage set point. the rise time of the voltage ramp can be programmed using the ton_ rise n command to minimize inrush currents associated with the start- up voltage ramp. the soft- start feature is disabled by setting ton_ rise n to any value less than 0.250ms. the ltm4675 performs the necessary math internally to assure the voltage ramp is controlled to the desired slope . however , the voltage slope can not be any faster than the fundamental limits of the power stage. the number of steps in the ramp is equal to ton_ rise/0.1ms. therefore, the shorter the ton_ rise n time setting, the more jagged the soft- start ramp appears. the ltm4675 pwm always operates in discontinuous mode during the ton_rise n operation. in discontinuous mode, the bottom mosfet (mbn) is turned off as soon as reverse current is detected in the inductor. this allows the regulator to start up into a pre-biased load. there is no analog tracking feature in the ltm4675; however , two outputs can be given the same ton _ rise n and ton_delay n times to achieve ratiometric rail tracking. because the run n pins are released at the same time and both units use the same time base (share_clk), the outputs track very closely. if the circuit is in a polyphase configuration, all timing parameters must be the same. table 8. recommended mfr_iin_offset n setting vs switching frequency setting switching frequency (khz) frequency_ switch command value (hex.) recommended mfr_iin_ offset n setting (ma) recommended mfr_iin_ offset n setting (hex.) 250 0xf3e8 20.26 0x8a98 350 0 xfabc 23.98 0x8b12 425 0xfb52 26.77 0x8b6d 500 0xfbe8 29.56 0x8bc9 575 0x023f 32.35 0x9212 650 0x028a 35.14 0x9240 750 0x02ee 38.86 0x927d 1000 0 x03e8 48.16 0x9315 sync. to external clock, f sync 0x0000 0.372 ? f sync + 10.96 * *see appendix c: pmbus command details, l11 data format. ltm 4675 4675f
52 for more information www.linear.com/ltm4675 dac voltage error (not to scale) time delay of many seconds digital servo mode enabled final output voltage reached ton_max_fault_limit n ton_rise n time 4675 f03 ton_dela y n v outn run n vout_uv_fault_limit n figure 3. timing controlled v out rise applications information coincident rail tracking can be achieved by setting two outputs to have the same turn-on/off slew rates, identical turn-on delays, and appropriately chosen turn-off delays: vout _command rail1 ton_rise rail1 = vout _command rail2 ton_rise rail2 and vout _command rail1 toff _fall rail1 = vout _command rail2 toff _fall rail2 and ton_delay rail1 = ton_ delay rail2 and (if vout_command rail2 vout_command rail1 ) toff _delay rail1 = toff _delay rail2 + 1C vout _command rail1 vout _command rail2 ? ? ? ? ? ? ?toff _fall rail2 or else ( vout _ command rail 2 < vout _ command rail 1 ) toff _delay rail2 = toff _delay rail1 + 1C vout _command rail2 vout _command rail1 ? ? ? ? ? ? ?toff _fall rail1 the described method of start - up sequencing is time based . for concatenated events it is possible to control the run pin based on the gpio n pin of a different controller (see figure 2). the gpio n pin can be configured to release when the output voltage of the converter is greater than the vout_uv_fault_limit n . it is recommended to use the unfiltered v out uv fault limit because there is little appreciable time delay between the converter crossing the uv threshold and the gpio n pin releasing. the unfiltered output can be enabled by the mfr _ gpio _ propagate n [12] setting . (refer to the mfr section of the pmbus commands in appendix c: pmbus command details). the unfiltered signal may have some glitching as the v out signal transitions through the comparator threshold. a small digital filter of 250s internally deglitches the gpio n pins. if the ton_rise time is greater than 100ms, the deglitch filter should be complimented with an externally applied capacitor between gpio n and groundto further filter the waveform. the rc time-constant of the filter should be set sufficiently fast to assure no appreciable delay is incurred. for most applications, a value of 300s to 500s will provide sufficient filtering without significantly delay- ing the trigger event. digital servo mode for maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the mfr_pwm_mode n command. in digital servo mode, the ltm 4675 adjusts the regulated output voltage based on the adc voltage reading. every 100ms the digital servo loop steps the lsb of the dac (nominally 1.375 mv or 0.6875 mv depending on the voltage range bit , mfr_pwm_mode n [1]) until the output is at the correct adc reading. at power-up this mode engages after ton_ max_fault_limit n unless the limit is set to ?0 ( infinite). if the ton_max_fault_limit n is set to 0 (infinite), the servo begins after ton_rise n is complete and v outn has exceeded vout_uv_fault _limit n and iout_oc n is not present. this same point in time is when the output changes from discontinuous to the mode commanded by mfr_pwm_mode n [0]. refer to figure 3 for details on the v outn waveform under time based sequencing. ltm 4675 4675f
53 for more information www.linear.com/ltm4675 applications information if the ton_max_fault_limit n is set to a value greater than 0 and the ton_max_fault_response n is set to ignore (0x00), the servo begins: 1. after the ton_rise n sequence is complete 2. after the ton_max_fault_limit n time is reached; and 3. after the vout_uv_fault_limit n has been exceed or the iout_oc_fault_limit n is no longer active. if the ton_max_fault_limit n is set to a value greater than 0 and the ton_max_fault_response n is not set to ignore (0x00), the servo begins: 1. after the ton_rise n sequence is complete; 2. after the ton_max_fault_limit n time has expired and both vout_uv_fault n and iout_oc_ fault n are not present. the maximum rise time is limited to 1.3 seconds. in a polyphase configuration it is recommended only one of the control loops have the digital servo mode enabled. this will assure the various loops do not work against each other due to slight differences in the reference circuits. soft off (sequenced off) in addition to a controlled start-up, the ltm4675 also supports controlled turn - off . the toff _ delay n and toff_fall n functions are shown in figure 4. toff_fall n is processed when the run n pin goes low or if the module is commanded off. if the module faults off or gpio n is pulled low externally and the module is programmed to respond to this (mfr_gpio_response n = 0 xc0), the output three - states ( becomes high impedance ) rather than exhibiting a controlled ramp. the output then decays as a function of the load. the output voltage operates as shown in figure 4 so long as the part is in forced continuous mode and the toff_fall n time is sufficiently slow that the power stage can achieve the desired slope. the toff_fall n time can only be met if the power stage and controller can sink sufficient current to assure the output is at zero volts by the end of the fall time interval. if the toff_fall n time is set shorter than the time required to discharge the load capacitance, the output will not reach the desired zero volt state. at the end of toff_fall n , the controller ceases to sink current and v outn decays at the natural rate determined by the load impedance. if the controller is in discontinuous mode, the controller does not pull negative current and the output becomes pulled low by the load, not the power stage. the maximum fail time is limited to 1.3 seconds . the number of steps in the ramp is equal to toff_fall/0.1ms.therefore, the shorter the toff_fall n setting, the more jagged the toff_ fall n ramp appears. undervoltage lockout the ltm 4675 is initialized by an internal threshold - based uvlo where sv in must be approximately 4v and intv cc , v dd 33 , v dd 25 must be within approximately 20% of the regulated values. in addition, v dd33 must be within approximately 7% of the targeted value before the ltm 4675 releases its run n pins. after the part has initialized, an additional comparator monitors sv in . the vin_on threshold must be exceeded before the power sequencing can begin . when sv in drops below the vin _ off threshold, the ltm4675 pulls its run n pins low and sv in must increase above the vin_on threshold before the controller will restart. the normal start-up sequence will be allowed after the vin_on threshold is crossed. it is possible to program the contents of the nvm in the application if the v dd33 supply is externally driven. this activates the digital portion of the ltm 4675 without engaging the high voltage sections . pmbus communications are valid in this supply configura - tion . if sv in has not been applied to the ltm 4675 , figure 4. toff_delay n and toff_ fall n toff_fall n toff_delay n time 4675 f04 v outn run n ltm 4675 4675f
54 for more information www.linear.com/ltm4675 applications information mfr_common[3] will be asserted low, indicating that nvm has not initialized. if this condition is detected, the part will only respond to addresses 0x5a and 0x5b. to initialize the part issue the following set of commands: global address 0x5b command 0xbd data 0x2b followed by global address 0x5b command 0xbd and data 0xc4. the part will now respond to the correct address . configure the part as desired then issue a store_user_all. when sv in is applied a mfr_reset or restore_user_all, command must be issued to allow the pwm to be enabled and valid adc conversions to be read. fault detection and handling the ltm4675 gpio n pins are configurable to indicate a variety of faults including ov/uv, oc, ot, timing faults , peak overcurrent faults. in addition the gpio n pins can be pulled low by external sources to indicate to the ltm4675 the presence of a fault in some other portion of the system. the fault response is configurable via pmbus command code names with a _response suffix and allows the following options: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_ delay n refer to appendix c and the pmbus specification for more details. the ov response is automatic and rapid. if an ov is de- tected, mtn is turned off and bgn is turned on, until the ov condition clears. fault logging is available on the ltm4675. the fault log- ging is configurable to automatically store data when a fault occurs that causes the unit to fault off. the header portion of the fault logging table contains peak values. it is possible to read these values at any time. this data will be useful while troubleshooting the fault. if the ltm4675 internal temperature is in excess of 85c or below 0c, the write into the nvm is not recommended. the data will still be held in ram, unless the 3.3v supply uvlo threshold is reached. if the die temperature exceeds 130c all nvm communication is disabled until the die temperature drops below 125c, with the exception of the restore_user_all command, which is valid at any temperature. open-drain pins note that up to nine pull-up resistors are required for proper operation of the ltm4675 : ? three for the smbus/i 2 c interface (the scl, sda, and alert pins); two, only if the system smbus host does not make use of the alert interrupt. (these are 5v tolerant). ? one each for the run 0 and run 1 pins (or, just one to run 0 and run 1 , if run 0 and run 1 are electrically connected together). (these are 5v tolerant). ? one each for gpio 0 and gpio 1 (or, just one to gpio 0 and gpio 1 , if gpio 0 and gpio 1 are electrically connected together). (these are 3.3v tolerant). ? one on share_clk, required, for the ltm4675 to establish a heartbeat time base for timing-related op- erations and functions (output voltage ramp-up timing, voltage margining transition timing, sync open-drain drive frequency). (share clk is 3.3v tolerant). ? one on sync, in order for the ltm4675 to phase lock to the frequency generated by the open-drain output of its digital engine. exception: in some applications, it is desirable to drive the ltm4675s sync pin with a hard-driven (low impedance) external clock. this is the only scenario where the ltm4675 does not require a pull-up resistor on sync. however, be aware that the sync pin can be low impedance during nvm initialization , i . e ., during download of eeprom contents to ram (for ~50ms [note 12] after sv in power is applied). therefore, the hard-driven clock signal should only be applied to the ltm4675 sync pin through a series resistor whose impedance limits current into the sync pin during nvm initialization to less than 10ma. if frequency _ switch =0 x 0000, any clock signal should be provided prior to the run n pins toggle from logic low to logic high, or else the switching frequency of the ltm4675 will start off at the low end of its pll- capture range (~225khz) until the sync clock becomes established. (sync is 3.3v tolerant). ltm 4675 4675f
55 for more information www.linear.com/ltm4675 applications information all the above pins interface to pull - down transistors within the module that can sink 3ma at 0.4v. the low threshold on the pins is 1.4v; thus, plenty of margin on the digital signals with 3 ma of current . for 3.3 v pins , 3ma of current is a 1.1k resistor. unless there are transient speed issues associated with the rc time constant of the resistor pull- up and parasitic capacitance to ground, a 10k resistor or larger is generally recommended. for high speed signals such as the sda, scl and sync, a lower value resistor may be required. the rc time con- stant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. for a 100pf load and a 400khz pmbus communication rate, the rise time must be less than 300 ns. the resistor pull-up on the sda and scl pins with the time constant set to 1/3 the rise time: r pullup = t rise 3 ?100pf = 1k be careful to minimize parasitic capacitance on the sda and scl pins to avoid communication problems. to estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. this is one time constant. the sync pin interfaces to a pull - down transis - tor within the module whose output is held low for nominally 500ns per switching period. if the internal oscillator is set for 500khz and the load is 100pf and a 3x time constant is required, the resistor calculation is as follows: r pullup = 2s C 500ns 3 ?100pf = 5k the closest 1% resistor is 4.99k. if timing errors are occurring or if the sync frequency is not as fast as desired , monitor the waveform and determine if the rc time constant is too long for the application. if possible reduce the parasitic capacitance. if not reduce the pull up resistor sufficiently to assure proper timing. phase-locked loop and frequency synchronization the ltm4675 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. the pll is locked to the falling edge of the sync pin. the phase relationship between channel 0, channel 1 and the falling edge of sync is controlled by the lower 3 bits of the mfr_pwm_config command. for polyphase applications, it is recommended all the phases be spaced evenly. thus for a 2-phase system the signals should be 180 out of phase and a 4-phase system should be spaced 90. the phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen- tary current sources that charge or discharge the internal filter network. the pll lock range is guaranteed between 225khz and 1.1mhz. the pll has a lock detection circuit. if the pll should lose lock during operation , bit 4 of the status _ mfr _ specific command is asserted and the alert pin is pulled low. the fault can be cleared by writing a 1 to the bit. if the user does not wish to see the pll_fault, even if a synchronization clock is not available at power up, bit 3 of the mfr_config_all command must be asserted. if the sync signal is not clocking in the application, the pll runs at the lowest free running frequency of the vco. this will be well below the intended pwm frequency of the application and may cause undesirable operation of the converter. if the pwm (swn) signal appears to be running at too high a frequency, monitor the sync pin. extra transitions on the falling edge will result in the pll trying to lock on to noise instead of the intended signal. review routing of digital control signals and minimize crosstalk to the sync signal to avoid this problem. multiple ltm4675s are required to share the sync pin in polyphase ltm 4675 4675f
56 for more information www.linear.com/ltm4675 applications information configurations; for other configurations, it is optional. if the sync pin is shared between ltm4675s, only one ltm4675 can be programmed with a frequency output. all the other ltm4675s must be configured for external clock (mfr_config_all[4]=1 b , and/or see table 4). rconfig pin-straps (external resistor configuration pins) the ltm4675 default nvm is programmed to respect the rconfig pins . if a user wishes the output voltage, pwm frequency and phasing and the address to be set without programming the part or purchasing specially programmed parts, the rconfig pins can be used to establish these parameters provided mfr _ config _ all[6] = 0 b . the rconfig pins only require a resistor terminating to sgnd of the ltm4675. the rconfig pins are only monitored at initial power up and during a reset ( mfr _ reset or restore _ user _ all ) so modifying their values perhaps using a dac after the part is powered will have no effect. to assure proper operation, the value of rconfig resistors applied to the ltm4675 pin-strapping pins must not deviate more than 3% away from the target nominal values indicated in lookup table 2 to table 5, over the lifetime of the product. thin film, 1% tolerance (or better), 50ppm/c-t.c.r. rated (or better) resistors from vendors such as koa speer, panasonic, vishay and yageo are good candidates. noisy clock signals should not be routed near these pins. note that bits [3:0] of mfr_ address are dictated by the asel pin- strap resistor regardless of the setting of mfr_config_all[6]. voltage selection when an output voltage is set using the rconfig pins on voutn_cfg and vtrimn_cfg (mfr_config_all[6] = 0 b ), the following parameters are set as a percentage of the output voltage: ? vout_ov_fault_limit +10% ? vout_ov_ warn +7.5% ? vout_max +7.5% ? vout_margin_hi +5% ? vout_margin_lo C5% ? vout_uv_ warn C6.5% ? vout_uv_fault_limit C7% connecting the usb to the i 2 c/smbus/pmbus controller to the ltm4675 in system the lt c usb to i 2 c/smbus/pmbus controller can be interfaced to the ltm4675 on the users board for pro- gramming, telemetry and system debug. the controller, when used in conjunction with ltpowerplay , provides a powerful way to debug an entire power system. faults are quickly diagnosed using telemetry , fault status registers and the fault log. the final configuration can be quickly developed and stored to the ltm4675 eeprom. ltm 4675 4675f
57 for more information www.linear.com/ltm4675 applications information figure 5 and figure 6 illustrate the application schematics for powering, programming and communicating with one or more ltm4675 s via the ltc i 2 c/smbus/pmbus controller regardless of whether or not system power is present. if system power is not present the dongle will power the ltm4675 through the v dd33 supply pin. to initialize the part when sv in is not applied and the v dd33 pin is powered use global address 0x5b command 0xbd data 0x2b followed by address 0x5b command 0xbd data 0xc4. the part can now be communicated with, and the project file updated. to write the updated project file to the nvm issue a store_user_all command. when sv in is applied, a mfr_reset or restore_user_all must be issued to allow the pwm to be enabled and valid adcs to be read. because of the controllers limited current sourcing capabil- ity, only the ltm4675s, their associated pull-up resistors and the i 2 c pull-up resistors should be powered from the ored 3.3v/3.4v supply. in addition, any device sharing the i 2 c bus connections with the ltm4675 must not have body diodes between the sda/scl pins and their respec- tive v dd node because this will interfere with bus com- munication in the absence of system power. in figure 5, the dongle will not bias the ltm4675s when sv in is present. it is recommended the run n pins be held low to avoid providing power to the load until the part is fully configured. the lt c controller/adapter i 2 c connections are opto- isolated from the pc usb. the 3.3v/3/4v from the control- ler/adapter and the ltm4675 v dd33 pin must be driven to each ltm4675 with a separate pfet or diode, according to figure 5 and figure 6. only when sv in is not applied is it permissible for the v dd33 pins to be electrically in parallel because the intv cc ldo is off. the dc1613s 3.3v current limit is 100ma but typical v dd33 currents are under 15ma. the v dd33 does back drive the intv cc pin. normally this is not an issue if sv in is open. the dc2086 is capable of delivering 3.4v at 2a. using a 4-pin header in figure 5 or figure 6 maximizes flexibility to alter the ltm4675 s nvm contents at any stage of the users product development and production cycles. if the ltm 4675 s nvm is pre - programmed , i . e ., contains its finalized configuration, prior to being soldered to the users pcb/motherboardor, if other means have been provided for altering the ltm4675's nvm contents in the users systemthen the 3.3v/3.4v pin on the header is not needed, and a 3-pin header is sufficient to establish gui communications. the ltm4675 can be purchased with customized nvm contents ; consult factory for details. alternatively, the nvm contents of the ltm4675 can be configured in a mass production environment by design- ing for it in ict (in- circuit test), or by providing a means of applying sv in while holding the ltm4675s run pins low . communication to the module must be made possible via the scl and sda pins/nets in all nvm programming scenarios. recommended headers are found in table 9 and table 10. ltm 4675 4675f
58 for more information www.linear.com/ltm4675 applications information figure 6. circuit suitable for programming eeprom/nvm of ltm4675 and other lt c psm modules/ics in vast systems, even when v in power is absent, t a > 20c and t j < 85c figure 5. circuit suitable for programming eeprom/nvm of ltm4675 and other lt c psm modules/ics in vast systems, even when v in power is absent, 0c < t j 85c sv in v in v dd33 v dd25 sda vgs max on the tp0101k is 8v. if v in > 16v, change the resistor divider on the pfet gate alternate pfets/packages: sot-723: good-ark semi ssf2319ge on semi ntk3139pt1g rohm rzm002p02t2l sot-523: diodes inc. dmg1013t-7 good-ark semi ssf2319gd sot-563: diodes inc. dmp2104v-7 on semi ntzs3151pt1g sot-323: diodes inc. dmg1013uw-7 on semi nts2101pt1g vishay si1303dl-t1-e3 4675 f05 10k 100k tp0101k sot-23 see tables 9-13 for connector and pinout options isolated 3.4v (usually needed) scl sda tp0101k sot-23 100k to ltc dc2086 digital power programming adapter (requires ltc dc1613 usb to i 2 c/smbus/ pmbus controller) module programming and communication interface header scl wp sgnd ltm4675 sv in v dd33 sda scl wp sgnd ltm4675 10k v dd25 sv in v in v dd33 v dd25 sda d1, d2: nxp pmeg2005ael or pmeg2005aeld. diode selection is not arbitrary. use v f < 210mv at i f = 20ma 4675 f06 10k see tables 9-13 for connector and pinout options isolated 3.4v (usually needed) scl d1 sod882 sda module programming and communication interface header to ltc dc2086 digital power programming adapter (requires ltc dc1613 usb to i 2 c/smbus/ pmbus controller) scl wp sgnd ltm4675 sv in v dd33 sda scl wp sgnd ltm4675 10k v dd25 d2 sod882 ltm 4675 4675f
59 for more information www.linear.com/ltm4675 applications information table 9. 4-pin headers, 2mm pin-to-pin spacing, gold flash or plating, compatible with dc2086 cables mounting style insertion angle interface style vendor part number pinout style (see table 11) surface mount vertical shrouded and keyed header hirose df3dz-4p-2v(51) df3dz-4p-2v(50) df3z-4p-2v(50) type a non shrouded, non-keyed header 3m 951104-2530-ar-pr type a and b supported. reversible/not keyed right angle shrouded and keyed header hirose df3dz-4p-2h(51) df3dz-4p-2h(50) type a non shrouded. cable-to-header/pcb mechanics yield keying effect fci 10112684-g03-04ulf type b. keying achieved by pcb surface through-hole vertical shrouded and keyed header hirose df3-4p-2dsa(01) type a non shrouded, non-keyed header harwin m22-2010405 type a and b supported. reversible/not keyed samtec tmm-104-01-ls sullins nrpn041 paen-rc right angle shrouded and keyed header hirose df3-4p-2ds(01) type a non shrouded. cable-to-header/pcb mechanics yield keying effect norcomp 27630402rp2 type b. keying achieved by intentional pcb interference harwin m22-2030405 samtec tmm-104-01-l-s-ra table 10. 3-pin headers, 2mm pin-to-pin spacing, gold flash or plating, compatible with dc2086 cables mounting style insertion angle interface style vendor part number pinout style (see table 12) surface mount vertical shrouded and keyed header hirose df3dz-3p-2v(51) df3dz-3p-2v(50) df3 z-3p-2v(50) type a non shrouded, non-keyed header 3m 951103-2530-ar-pr type a and b supported. reversible/not keyed right angle shrouded and keyed header hirose df3dz-3p-2h(51) df3dz-3p-2h(50) type a non shrouded. cable-to-header/pcb mechanics yield keying effect fci 10112684-g03-03lf type b. keying achieved by pcb surface through-hole vertical shrouded and keyed header hirose df3-3p-2dsa(01) type a non shrouded, non- keyed header harwin m22-2010305 type a and b supported. reversible/not keyed samtec tmm-103-01-ls sullins nrpn031 paen-rc right angle shrouded and keyed header hirose df3-3p-2ds(01) type a non shrouded. cable-to-header/pcb mechanics yield keying effect norcomp 27630302rp2 type b. keying achieved by intentional pcb interference harwin m22-2030305 samtec tmm-103-01-l-s-ra table 11. recommended 4-pin header pinout (pin numbering scheme adheres to hirose conventions). interfaces to dc2086 cables pin number pinout style a (see table 9) pinout style b (see table 9) 1 sda isolated 3.3v/3.4v 2 gnd scl 3 scl gnd 4 isolated 3.3v/3.4v sda table 12. recommended 3-pin header pinout (pin numbering scheme adheres to hirose conventions). interfaces to dc2086 cables pin number pinout style a (see table 10) pinout style b (see table 10) 1 sda scl 2 gnd gnd 3 scl sda ltm 4675 4675f
60 for more information www.linear.com/ltm4675 applications information ltpowerplay : an interactive gui for digital power system management ltpowerplay is a powerful windows-based development environment that supports linear technology digital power ics including the ltm 4675 . the software supports a variety of different tasks. ltpowerplay can be used to evaluate linear technology ics by connecting to a demo board or the user application . ltpowerplay can also be used in an offline mode (with no hardware present) in order to build multiple figure 7. ltpowerplay ic configuration files that can be saved and reloaded at a later time . ltpowerplay provides unprecedented diagnostic and debug features. it becomes a valuable diagnostic tool during board bring-up to program or tweak the power system or to diagnose power issues when bringing up rails. ltpowerplay utilizes linear technology s usb- to- i 2 c / smbus/pmbus controller to communication with one of the many potential targets including the dc2053 (single ltm4675), dc1811 (single ltm4676a) or dc1989 (dual, triple, quad ltm4676) demo boards, or a customer target system. the software also provides an automatic update feature to keep the revisions current with the latest set of device drivers and documentation. a great deal of context sensitive help is available with ltpowerplay along with several tutorial demos . complete information is available at http://www.linear.com/ltpowerplay table 13. 4-pin male-to-male shrouded and keyed adapter (optional. eases creation of adapter cables, if deviating from recommended connectors/connector pinouts). interfaces to dc2086 cables vendor part number website hirose df3-4ep-2a www.hirose.com, www.hirose.co.jp ltm 4675 4675f
61 for more information www.linear.com/ltm4675 applications information pmbus communication and command processing the ltm4675 has one deep buffer to hold the last data written for each supported command prior to processing as shown in figure 8; write command data processing. when the part receives a new command from the bus, it copies the data into the write command data buffer, indicates to the internal processor that this command data needs to be fetched, and converts the command to its internal format so that it can be executed. tw o distinct parallel blocks manage command buffering and command processing (fetch, convert, and execute) to ensure the last data written to any command is never lost. command data buffering handles incoming pm- bus writes by storing the command data to the write command data buffer and marking these commands for future processing. the internal processor runs in parallel and handles the sometimes slower task of fetching, con- verting and executing commands marked for processing . some computationally intensive commands (e.g., timing parameters, temperatures, voltages and currents) have internal processor execution times that may be long relative to pmbus timing. if the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. the part indicates when internal calculations are in process via bit ?5 of mfr_common (calculations not pending). when the part is busy calculating, bit 5 is cleared. when this bit is set, the part is ready for another command. an example polling loop is provided in figure 8 which ensures that commands are processed in order while simplifying error handling routines. when the part receives a new command while it is busy, it will communicate this condition using standard pmbus protocol. depending on part configuration it may either nack the command or return all ones (0xff) for reads. it may also generate a busy fault and alert notification, or stretch the scl clock low. for more information refer to pmbus specification v1.2, part ii, section 10.8.7 and smbus v2.0 section 4.3.3. clock stretching can be enabled by asserting bit 1 of mfr_config_all. clock stretching will only occur if enabled and the bus communication speed exceeds 100khz. pmbus busy protocols are well accepted standards, but can make writing system level software somewhat com- plex. the part provides three hand shaking status bits which reduce complexity while enabling robust system level communication. the three hand shaking status bits are in the mfr_ common register. when the part is busy executing an internal operation, it will clear bit 6 of mfr_common (module not busy). when the part is busy specifically because it is in a transitional vout state (margining hi/lo, power off/on, moving to a new output voltage set point, etc.) it will clear bit 4 of mfr_common (output not in transition). when internal calculations are in process, the part will clear bit ?5 of mfr_common (calculations not pending). these three status bits can be polled with a pmbus read byte of the mfr_common register until all three bits are set. a command immediately following the status bits being set will be accepted without nacking or generating a busy fault/alert notification. the part can nack commands for other reasons, however , as required by the pmbus spec (for instance, an invalid command or data). an example of a robust command write algorithm for the vout_ command n register is provided in figure 9 . decoder cmd internal processor write command data buffer page cmds 0x00 0x21 0xfd 4675 f08 x1 mfr_reset vout_command s calculations pending pmbus write r fetch, convert data and execute data mux figure 8. write command data processing figure 9. example of a command write of vout_command // wait until bits 6, 5, and 4 of mfr_common are all set do { mfrcommonvalue = pmbus_read_byte(0xef); partready = (mfrcommonv alue & 0x68) == 0x68; }while (!partready) // now the part is ready to receive the next command pmbus_write_word(0x21, 0x2000); //write vout_command to 2v ltm 4675 4675f
62 for more information www.linear.com/ltm4675 applications information it is recommended that all command writes (write byte, write word, etc.) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted alert notification. a simple way to achieve this is by creating safe_write_byte() and safe_write_ word () subroutines . the above polling mechanism allows ones software to remain clean and simple while robustly communicating with the part. for a detailed discussion of these topics and other special cases please refer to the application note section located at www.linear.com/ designtools/app_notes. when communicating using bus speeds at or below 100khz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. at bus speeds in excess of 100khz, it is strongly recommended that the part be configured to en- able clock stretching. this requires a pmbus master that supports clock stretching. system software that detects and properly recovers from the standard pmbus nack/ busy faults as described in the pmbus specification v1.2, part ii, section 10.8.7 is required to communicate above 100khz without clock stretching. clock stretching will not extend the pmbus speed beyond the specified 400khz. thermal considerations and output current derating the thermal resistances reported in the pin configura- tion section of this data sheet are consistent with those parameters defined by jesd51-12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per - formed on a module package mounted to a hardware test board defined by jesd51-9 ( test boards for area array surface mount package thermal measurements). the motivation for providing these thermal coefficients is found in jesd51-12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the module regulators thermal performance in their application at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin configuration section are in-and-of themselves not relevant to providing guidance of thermal performance ; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section gives four thermal coeffi- cients explicitly defined in jesd51-12; these coefficients are quoted or paraphrased below: 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board , which does not reflect an actual application or viable operating condition. 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the pack- age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis- tance where almost all of the heat flows through the bottom of the module regulator and into the board, and is really the sum of the jcbottom and the thermal ltm 4675 4675f
63 for more information www.linear.com/ltm4675 applications information resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd51-9. a graphical representation of the aforementioned thermal resistances is given in figure 10; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd51-12 or provided in the pin configuration section replicates or conveys normal op- erating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss ( heat) thermally conduct exclusively through the top or exclusively through bot- tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow , a majority of the heat flow is into the board. within the ltm4675, be aware there are multiple power devices and components dissipating power, with a con- sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicity but also , not ignoring practical realities an approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reason- ably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the ltm4675 and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined jedec environment consistent with jsed 51-9 and jesd51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the ltm4675 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled envi- ronment chamber while operating the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well - correlated jesd 51-12- defined values provided in the pin configuration section of this data sheet. the 1 v , 1.8 v and 3.3 v power loss curves in figure 11 , figure 12 and figure 13 respectively can be used in coordination with the load current derating curves in figures 14 to 25 for calculating an approximate ja thermal resistance for the ltm 4675 with various heat sinking and air flow conditions . these thermal resistances represent demonstrated performance of the ltm 4675 4675 f10 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance figure 10. graphical representation of jesd51-12 thermal coefficients ltm 4675 4675f
64 for more information www.linear.com/ltm4675 applications information on dc 2053 a hardware ; a 4- layer fr 4 pcb measuring 99 mm 133 mm 1.6 mm using outer and inner copper weights of 2 oz and 1 oz , respectively . the power loss curves are taken at room temperature , and are increased with multiplicative factors with ambient temperature . these approximate factors are listed in table 14 . ( compute the factor by interpolation , for intermediate temperatures .) the derating curves are plotted with the ltm 4675 s paralleled outputs initially sourcing up to 18 a and the ambient temperature at 30 c . the output voltages are 1 v , 1.8 v and 3.3 v . these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance . thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis . the junction temperatures are monitored while ambient temperature is increased with and without air flow , and with and without a heat sink attached with thermally conductive adhesive tape . the power loss increase with ambient temperature change is factored into the derating curves . the junctions are maintained at 120 c maximum while lowering output current or power while increasing ambient temperature . the decreased output current decreases the internal module loss as ambient temperature is increased . the monitored junction temperature of 120 c minus the ambient operating temperature specifies how much module temperature rise can be allowed . as an example in figure 19 , the load current is derated to ~12 a at ~65 c ambient with 200 lfm airflow and no heat sink and the room temperature (25 c ) power loss for this 12 v in to 1 v out at 12 a out condition is ~3.6 w . a 4.05 w loss is calculated by multiplying the ~3.6 w room temperature loss from the 12 v in to 1.8 v out power loss curve at 12 a ( figure 12 ), with ? the 1.125 multiplying factor at 65 c ambient ( from table 14 ). if the 65 c ambient temperature is subtracted from the 120 c junction temperature , then the difference of 55 c divided by 4.05 w yields a thermal resistance , ja , of 13.6 c / w in good agreement with table 16 . table 15 , table 16 and table 17 provide equivalent thermal resistances for 1 v , 1.8 v and 3.3 v outputs with and without air flow and heat sinking . the derived thermal resistances in table 15 , table 16 and table 17 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient , thus maximum junction temperature . room temperature power loss can be derived from the efficiency curves in the typical performance characteristics section and adjusted with ambient temperature multiplicative factors from table 14 . table 14. power loss multiplicative factors vs ambient temperature ambient temperature power loss multiplicative factor up to 40c 1.00 50c 1.05 60c 1.10 70c 1.15 80c 1.20 90c 1.25 100c 1.30 110c 1.35 120c 1.40 ltm 4675 4675f
65 for more information www.linear.com/ltm4675 applications information table 15. 1.0v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 14, 15 5, 12 figure 11 0 none 16.1 figures 14, 15 5, 12 figure 11 200 none 12.3 figures 14, 15 5, 12 figure 11 400 none 11.2 figures 16, 17 5, 12 figure 11 0 bga heat sink 14.8 figures 16, 17 5, 12 figure 11 200 bga heat sink 11.4 figures 16, 17 5, 12 figure 11 400 bga heat sink 10.3 table 16. 1.8v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 18, 19 5, 12 figure 12 0 none 16.4 figures 18, 19 5, 12 figure 12 200 none 13.4 figures 18, 19 5, 12 figure 12 400 none 12.3 figures 20, 21 5, 12 figure 12 0 bga heat sink 15.4 figures 20, 21 5, 12 figure 12 200 bga heat sink 12.6 figures 20, 21 5, 12 figure 12 400 bga heat sink 11.4 table 17. 3.3v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figure 22, 23 5, 12 figure 13 0 none 15.9 figure 22, 23 5, 12 figure 13 200 none 13.1 figure 22, 23 5, 12 figure 13 400 none 11.8 figure 24, 25 5, 12 figure 13 0 bga heat sink 15.0 figure 24, 25 5, 12 figure 13 200 bga heat sink 12.2 figure 24, 25 5, 12 figure 13 400 bga heat sink 11.1 table 18. heat sink manufacturer (thermally conductive adhesive tape pre-attached) heat sink manufacturer part number website cool innovations 3-050435ut411 www.coolinnovations.com table 19. thermally conductive adhesive tape vendor thermally conductive adhesive tape manufacturer part number website chomerics t411 www.chomerics.com ltm 4675 4675f
66 for more information www.linear.com/ltm4675 applications information table 20. ltm4675 channel output voltage response vs component matrix. 4.5a load- stepping at 4.5a /s . typical measured values c outh vendors part number c outl vendors part number avx 12106d107 mat 2a (100f, 6.3v, 1210 case size) sanyo poscap 6tpf330m9l (330f, 6.3v, 9m esr, d3l case size) murata grm32er60j107me20l (100f, 6.3v, 1210 case size) sanyo poscap 6tpd470m (470f, 6.3v, 10m esr, d4d case size) taiyo yuden jmk325bj107mm-t (100f, 6.3v, 1210 case size) sanyo poscap 2r5tpe470m9 (470f, 2.5v, 9m esr, d2e case size) tdk c3225x5r0j107mt (100f, 6.3v, 1210 case size) sanyo poscap 6tpf470mah (470f, 6.3v, 10m esr, d4 case size) v outn (v) v inn (v) ref. circuit* c outhn (ceramic output cap) c outln (bulk output cap) connect comp n a to comp n b ? (internal loop comp) r thn (ext loop comp) (k) c thn (ext loop comp) (nf) f sw (khz) f swphcfg pin- strap, resistor to sgnd ( table 4) (k) v outn cfg pin- strap resistor to sgnd ( table 2) (k) v trimn cfg pin- strap, resistor to sgnd ( table 3) (k) trans- ient droop (0a to 4.5a) (mv) pk-pk devi- ation (0a to 4.5a to 0a) (mv) recov- ery time (s) 0.9 5 test ckt. 2 100f 4 none yes , cf. figure 60 n/a n/a 425 18.0 1.65 none 37 76 45 0.9 5 test ckt. 2 100f 3 470f yes , cf. figure 60 n/a n/a 425 18.0 1.65 none 30 63 50 0.9 12 test ckt. 1 100f 4 none yes , cf. figure 60 n/a n/a 425 18.0 1.65 none 37 76 45 0.9 12 test ckt. 1 100f 3 470f yes , cf. figure 60 n/a n/a 425 18.0 1.65 none 30 63 50 1 5 test ckt. 2 100f 4 none yes , cf. figure 60 n/a n/a 500 none 2.43 0 39 79 45 1 5 test ckt. 2 100f 3 470f yes , cf. figure 60 n/a n/a 500 none 2.43 0 31 63 50 1 12 test ckt. 1 100f 4 none yes , cf. figure 60 n/a n/a 500 none 2.43 0 39 79 45 1 12 test ckt. 1 100f 3 470f yes , cf. figure 60 n/a n/a 500 none 2.43 0 31 63 50 1.2 5 test ckt. 2 100f 4 none yes , cf. figure 60 n/a n/a 500 none 3.24 0 40 80 45 1.2 5 test ckt. 2 100f 3 470f yes , cf. figure 60 n/a n/a 500 none 3.24 0 32 64 50 1.2 12 test ckt. 1 100f 4 none yes , cf. figure 60 n/a n/a 575 15.4 3.24 0 40 80 45 1.2 12 test ckt. 1 100f 3 470f yes , cf. figure 60 n/a n/a 575 15.4 3.24 0 32 64 50 1.5 5 test ckt. 2 100f 4 none yes , cf. figure 60 n/a n/a 575 15.4 4.22 none 41 81 45 1.5 5 test ckt. 2 100f 3 470f yes , cf. figure 60 n/a n/a 575 15.4 4.22 none 32 65 50 1.5 12 test ckt. 1 100f 4 none yes , cf. figure 60 n/a n/ a 650 12.7 4.22 none 41 81 45 1.5 12 test ckt. 1 100f 3 470f yes , cf. figure 60 n/a n/a 650 12.7 4.22 none 32 65 50 1.8 5 test ckt. 2 100f 4 none yes , cf. figure 60 n/a n/a 650 12.7 6.34 0 41 82 45 1.8 5 test ckt. 2 100f 3 470f yes , cf. figure 60 n/a n/a 650 12.7 6.34 0 32 65 50 1.8 12 test ckt. 1 100f 4 none yes , cf. figure 60 n/a n/a 750 10.7 6.34 0 41 82 45 1.8 12 test ckt. 1 100f 3 470f yes , cf. figure 60 n/a n/a 750 10.7 6.34 0 32 65 50 2.5 5 test ckt. 2 100f 4 none yes , cf. figure 60 n/a n/a 650 12.7 10.7 none 42 87 45 2.5 5 test ckt. 2 100f 3 470f yes , cf. figure 60 n/a n/a 650 12.7 10.7 none 32 65 50 2.5 12 test ckt. 1 100f 4 none yes , cf. figure 60 n/a n/a 1000 9.09 10.7 none 42 87 45 2.5 12 test ckt. 1 100f 3 470f yes , cf. figure 60 n/a n/a 1000 9.09 10.7 none 32 65 50 3.3 5 test ckt. 2 100f 4 none yes , cf. figure 60 n/a n/a 650 12.7 22.6 none 70 147 50 3.3 5 test ckt. 2 100f 3 470f yes , cf. figure 60 n/a n/a 650 12.7 22.6 none 54 104 60 3.3 12 test ckt. 1 100f 4 none yes , cf. figure 60 n/a n/a 1000 9.09 22.6 none 70 147 50 3.3 12 test ckt. 1 100f 3 470f yes , cf. figure 60 n/a n /a 1000 9.09 22.6 none 54 105 60 5 12 test ckt. 1 100f 3 470f yes , cf. figure 60 n/a n/a 1000 9.09 32.4 7.68 56 113 60 *for all conditions: c inh input capacitance is 10f 2, per channel (v in0 , v in1 ). c inl bulk input capacitance of 150f is optional if v in has very low input impedance. ltm 4675 4675f
67 for more information www.linear.com/ltm4675 figure 11. 1v out power loss curve figure 12. 1.8v out power loss curve figure 13. 3.3v out power loss curve output current (a) 0 2 4 power loss (w) 4 6 4675 f11 2 0 6 8 10 12 14 16 18 7 5v in 3 5 1 8v in 12v in output current (a) 0 2 4 power loss (w) 4 6 4675 f12 2 0 6 8 10 12 14 16 18 7 5v in 3 5 1 8v in 12v in output current (a) 0 2 4 power loss (w) 4 6 4675 f13 2 0 6 8 10 12 14 16 18 7 5v in 3 5 1 8v in 12v in applications information- derating curves ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f17 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm figure 14. 5v to 1v derating curve , no heat sink figure 15. 12v to 1v derating curve, no heat sink ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f14 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f15 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f16 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm see also figure 35, 12v in to 5v out derating curves. figure 16. 5v to 1v derating curve , with heat sink figure 17. 12v to 1v derating curve , with heat sink ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f18 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f19 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm figure 18. 5v to 1.8v derating curve , no heat sink figure 19. 12v to 1.8v derating curve , no heat sink ltm 4675 4675f
68 for more information www.linear.com/ltm4675 applications information- derating curves ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f20 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f21 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm figure 20. 5v to 1.8v derating curve , with heat sink figure 21. 12v to 1.8v derating curve , with heat sink ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f23 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f24 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f25 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm ambient temperature (c) 30 0 maximum load current (a) 2 6 8 10 18 14 40 50 60 70 4675 f22 4 16 12 80 120 90 100 110 400lfm 200lfm 0lfm figure 22. 5v to 3.3v derating curve , no heat sink figure 23. 12v to 3.3v derating curve , no heat sink figure 24. 5v to 3.3v derating curve , with heat sink figure 25. 12v to 3.3v derating curve , with heat sink ltm 4675 4675f
69 for more information www.linear.com/ltm4675 applications information emi performance the sw n pin provides access to the midpoint of the power mosfets in ltm4675s power stages. connecting an optional series rc network from sw n to gnd can dampen high frequency (~30mhz+) switch node ringing caused by parasitic inductances and capacitances in the switched-current paths. the rc network is called a snubber circuit because it dampens (or snubs) the resonance of the parasitics, at the expense of higher power loss. to use a snubber, choose first how much power to allocate to the task and how much pcb real estate is available to implement the snubber. for example, if pcb space al- lows a low inductance 1w resistor to be usedderated conservatively to 600mw ( p snub )then the capacitor in the snubber network (c sw ) is computed by : c sw = p snub v in n (max) 2 f sw where v inn (max) is the maximum input voltage that the input to the power stage (v inn ) will see in the application, and f sw is the dc/dc converters switching frequency of operation. c sw should be npo, c0g or x7r-type (or better) material. the snubber resistor (r sw ) value is then given by: r sw = 5nh c sw the snubber resistor should be low esl and capable of withstanding the pulsed currents present in snubber cir - cuits. a value between 0.7 and 4.2 is normal. safety considerations the ltm4675 modules do not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top mosfet fault. if the internal top mosfet fails, then turning it off will not resolve the overvoltage , thus the internal bottom mosfet will turn on indefinitely trying to protect the load. under this fault condition, the input volt- age will source very large currents to ground through the failed internal top mosfet and enabled internal bottom mosfet. this can cause excessive heat and board dam- age depending on how much power the input voltage can deliver to this system. a fuse or circuit breaker can be used as a secondary fault protector in this situation. the device does support over current and overtemperature protection . layout checklist/example the high integration of ltm4675 makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance , some layout consid- erations are still necessary. ? use large pcb copper areas for high current paths, including v inn , gnd and v outn . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci- tors next to the v inn , gnd and v outn pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the module. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ltm 4675 4675f
70 for more information www.linear.com/ltm4675 ? do not put vias directly on pads, unless they are capped or plated over. ? use a separate sgnd copper plane for components connected to signal pins. connect sgnd to gnd local to the ltm4675. ? for parallel modules, tie the v outn , v osns0 + / v osns C and/ or v osns1 /sgnd voltage-sense differential pair lines, applications information figure 26. recommended pcb layout package top view run n , gpio n , comp n a , sync and share_clk pins togetheras shown in figure 31. ? bring out test points on the signal pins for monitoring. figure 26 (a) shows a good example of the ltm4675s recommended layout. for flexibility, the ltm4675 is drop- in pin-compatible to its taller, larger dual 13a ltm4676/ ltm4676a sibling modulesas seen in the layout recom- mended by figure 26 (b). 1 2 3 4 5 6 7 8 9 mlkjhgfedcba sgnd 9 8 7 6 5 c out0 gnd c out1 c in1 c in0 v in0 v in1 gnd gnd 4 3 2 1 a b c d e f g gnd v out1 v out0 h j k l m v out0 v in0 gnd gnd gnd sgnd gnd gnd gnd gnd gnd v out1 v in1 sgnd 9 8 7 6 5 c out0 gnd c out1 c in1 c in0 v in0 v in1 gnd gnd 4 3 2 1 a b c d e f g cntrl v out1 4675 f26ab v out0 h j k l m (a) pcb layout for ltm4675, package top view (b) pcb layout to accommodate any of ltm4675 or ltm4676 or ltm4676a modules 9 8 7 6 5 4 3 2 1 v in0 v in1 v out0 v out1 a b c d e f g h j k l m gnd gnd gnd gnd gnd ltm 4675 4675f
71 for more information www.linear.com/ltm4675 typical applications figure 27. 18a, 1.5v output dc/dc module regulator with i 2 c/smbus/pmbus serial interface (28a) 5v in , figure 27 circuit (28b) 12v in , figure 27 circuit with intv cc open and v out commanded to 1v total output current (a) 0 channel output current (a) 6 4675 f28a 6 2 2 4 8 0 ?2 10 i out0 i out1 8 4 10 12 14 18 total output current (a) 0 channel output current (a) 6 4675 f28b 6 2 2 4 8 0 ?2 10 i out0 i out1 8 4 10 12 14 18 figure 28. current sharing performance of the ltm4675's channels c inh 22f 3 c inl 220f 10k 7 v in 4.5v to 5.75v pwm clock synch. time base synch. slave address = 1001010_r/w (0x4a) 575 khz switching frequency no gui configuration and no part-specific programming required except: vin_off < vin_uv_warn_limit < vin_on < 4.3v in multi-module systems, configuring rail_address is recommended setting mfr_pwm_config[7]=1 b , configures the v out1 control loop to use the v osns0 + /v osns0 ? differential- sense pin-pair as the feedback signal for regulating v out1 . c out 100f 6 470f 10m esr 2 v out , 1.5v adjustable up to 18a v in0 v in1 sv in v dd33 load scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b gnd wp 10.7k 1% 50ppm/c 15.4k 1% 50ppm/c ltm4675 4675 f27 + 2.1k 1% 50ppm/c smbus interface with pmbus command set on/off control, fault management, power sequencing f swphcfg asel v out0 tsns 0 v orb0 + v osns0 + v osns0 ? v orb0 ? v orb1 v out1 tsns 1a tsns 1b v osns1 sgnd + ltm 4675 4675f
72 for more information www.linear.com/ltm4675 typical applications figure 29. 9a, 1.2v and 2.5v outputs generated from 3.3v power input and providing i 2 c/smbus/pmbus serial interface figure 30. output voltage margining, figure 29 circuit v out1 , 2.5v adjustable up to 9a c inh 22f 3 c inl 220f 10k 9 3.3v in nominal 5v low power bias <100ma pwm clock synch. time base synch. slave address = 1001111_r/w (0x4f) 500khz switching frequency no gui configuration and no part-specific programming required except: vin_off < vin_uv_warn_limit < vin_on < 4.5v in multi-module systems, configuring rail_address is recommended c out0 100f 5 c out1 100f 5 v out0 , 1.2v adjustable up to 9a v in0 v in1 sv in v dd33 load 0 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b gnd wp 3.24k 1% 50ppm/c ltm4675 4675 f29 + 10.7k 1% 50ppm/c smbus interface with pmbus command set on/off control, fault management, power sequencing load 1 f swphcfg asel v out0 tsns 0 v orb0 + v osns0 + v osns0 ? v orb0 ? v orb1 v out1 tsns 1a tsns 1b v osns1 sgnd (30a) pmbus operation (reg. 0x01): 0x80 0xa8 (margin high) (30c) pmbus operation (reg. 0x01): 0x80 0x98 (margin low) (30b) pmbus operation (reg. 0x01): 0xa8 0x80 (margin off) (30d) pmbus operation (reg. 0x01): 0x98 0x80 (margin off) v out1 50mv/div v out0 50mv/div scl 5v/div sda 5v/div 4ms/div 4675 f30a v out1 50mv/div v out0 50mv/div scl 5v/div sda 5v/div 4ms/div 4675 f30b v out1 50mv/div v out0 50mv/div scl 5v/div sda 5v/div 4ms/div 4675 f30c v out1 50mv/div v out0 50mv/div scl 5v/div sda 5v/div 4ms/div 4675 f30d ltm 4675 4675f
73 for more information www.linear.com/ltm4675 typical applications c in1 10f 4 c in5 150f 10k 7 v in 5.75v to 16v pwm clock synch. time base synch. c out(mlcc) 100f 10 c out(bulk) 330f 10 v out , 1v adjustable up to 70a v out0 tsns 0 v osns0 + v osns0 ? v ino v in1 sv in v dd33 load scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk asel f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b gnd wp u1 ltm4675 + smbus interface with pmbus command set u1: slave address = 1000000_r/w (0x40) u2: slave address = 1000001_r/w (0x41) u3: slave address = 1000010_r/w (0x42) u4: slave address = 1000011_r/w (0x43) 500khz switching frequency with interleaving no gui configuration and no part-specific programming required in multi-module systems, configuring rail_address is recommended electrically unconnected pins v orb0 + , v orb0 ? and v orb1 not shown setting mfr_pwm_config[7] = 1 b , configures the v out1 control loop to use the v osns0 + /v osns0 ? differential- sense pin-pair as the feedback signal for regulating v out1 . on/off control, fault management, power sequencing c in2 10f 4 v out0 tsns 0 v osns0 + v osns0 ? v ino v in1 sv in v dd33 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b gnd wp 1.65k 1% 50ppm/c 787 1% 50ppm/c u2 ltm4675 asel c in3 10f 4 v out0 tsns 0 v osns0 + v osns0 ? v ino v in1 sv in v dd33 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b gnd wp 3.24k 1% 50ppm/c 1.65k 1% 50ppm/c u3 ltm4675 asel c in4 10f 4 v out0 tsns 0 v osns0 + v osns0 ? v ino v in1 sv in v dd33 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b gnd wp 2.43k 1% 50ppm/c 4675 f31 c thp 220pf c th 3.3nf r th 1.65k u4 ltm4675 asel v out1 tsns 1a tsns 1b v osns1 sgnd v out1 tsns 1a tsns 1b v osns1 sgnd v out1 tsns 1a tsns 1b v osns1 sgnd v out1 tsns 1a tsns 1b v osns1 sgnd figure 31. four paralleled ltm4675 producing 1v out at up to 70a. integrated power system management features accessible over 2-wire i 2 c/smbus/pmbus serial interface. evaluated on dc1989a-c, custom-stuffed with ltm4675 modules ltm 4675 4675f
74 for more information www.linear.com/ltm4675 typical applications c in1 10f 4 c in5 150f 10k 6 12v in 20% c in2 10f 4 c out(mlcc) 100f 20 c out(bulk) 470f 10 v out , 1v adjustable up to 92a~122a v out0 tsns 0 v osns0 + v osns0 ? v ino v in1 sv in v dd33 load scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk asel f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b gnd wp u1 ltm4675 u2* + v out1 tsns 1a tsns 1b v osns1 sgnd pwm clock synch. time base synch. smbus interface with pmbus command set on/off control, fault management, power sequencing r th * c th * c intvcc2 4.7f u1: slave address = 1000000_r/w (0x40) 500khz switching frequency with interleaving no gui configuration and no part-specific programming required except: iout_oc_warn_limit n =18a mfr_gpio_response n = 0x00 in multi-module systems, configuring rail_address is recommended electrically unconnected pins v orb0 + , v orb0 ? and v orb1 not shown setting mfr_pwm_config[7] = 1 b , configures the v out1 control loop to use the v osns0 + /v osns0 ? differential- sense pin-pair as the feedback signal for regulating v out1 . r clk 200 m1 2n7002a 1.2k 1% 50ppm/c 6.34k 1% 50ppm/c r temp2 121k r vfb 8.25k r fset2 121k r div1 * r div2 * c in3 10f 4 c in4 10f 4 ? + u5a 1/2 lt1801 v in temp extv cc phasmd run1 run2 track1 track2 pgood1 v out1 v outs1 v fb1 v out2 v outs2 v fb2 diffp diffn diffout mode_pllin sw1 sw2 intv cc clkout sgnd gnd pgood2 comp1 comp2 f set u3* c intvcc3 4.7f r temp3 121k r fset3 121k temp extv cc phasmd run1 run2 track1 track2 pgood1 v out1 v outs1 v fb1 v out2 v outs2 v fb2 diffp diffn diffout mode_pllin sw1 sw2 intv cc clkout sgnd gnd pgood2 comp1 comp2 f set u4* c intvcc4 4.7f r temp4 121k r fset4 121k temp extv cc phasmd run1 run2 track1 track2 pgood1 v out1 v outs1 v fb1 v out2 v outs2 v fb2 diffp diffn diffout mode_pllin sw1 sw2 intv cc clkout sgnd gnd pgood2 4675 f32 comp1 comp2 f set ? + u5b 1/2 lt1801 demo board dc2106a-a dc2106a-b output current up to 92a up to 122a u2, u3, u4 ltm4620a ltm4630 u1 ltm4675 ltm4675 r div1 28k 23.2k r div2 90.9k 95.3k r th 13.3k 8.87k c th 4.7nf 4.7nf *stuffing options figure 32. one ltm4675 operating in parallel with 3 x ltm4620a or 3 x ltm4630 ( see demo boards dc2106a - a , dc2106a - b , custom- stuffed with ltm4675 modules for u 1) producing 1 v out at up to 92a ~ 122a . power system management features accessible through ltm4675. see figure 33 ltm 4675 4675f
75 for more information www.linear.com/ltm4675 typical applications (33a) ltm4675 paralleled with 3x ltm4620a (up to 92a output) (33b) ltm4675 paralleled with 3x ltm4630 (up to 122a output) figure 33. current sharing performance of figure 32 circuit at 12v in total output current (a) 0 channel output current (a) 6 8 10 9080 4675 f33a 4 2 ?2 20 40 60 10 100 30 50 70 0 14 12 u1-ltm4675-i out0 u1-ltm4675-i out1 u2-ltm4620a-i out1 u2-ltm4620a-i out2 u3-ltm4620a-i out1 u3-ltm4620a-i out2 u4-ltm4620a-i out1 u4-ltm4620a-i out2 total output current (a) 0 channel output current (a) 18 60 4675 f33b 9 3 20 40 80 0 ?3 21 15 12 6 100 120 140 u1-ltm4675-i out0 u1-ltm4675-i out1 u2-ltm4630-i out1 u2-ltm4630-i out2 u3-ltm4630-i out1 u3-ltm4630-i out2 u4-ltm4630-i out1 u4-ltm4630-i out2 ltm 4675 4675f
76 for more information www.linear.com/ltm4675 typical applications c inh 22f 3 c inl 220f 10k 7 v in 5.75v to 17v pwm clock synch. time base synch. slave address = 1000101_r/w (0x45) 1mhz switching frequency no gui configuration and no part-specific programming required in multi-module systems, configuring rail_address is recommended. setting mfr_pwm_config[7]=1 b , configures the v out1 control loop to use the v osns0 + /v osns0 ? differential- sense pin-pair as the feedback signal for regulating v out1 . c out 100f 10 v out , 5v adjustable up to 18a optional: installing u2 away from heat sources allows intv cc ldo losses normally incurred by the ltm4675 to be dissipated instead by the lt3060. thermal-derating can thus be improved v in0 v in1 sv in v dd33 load scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b gnd wp 4.22k 1% 50ppm/c 9.09k 1% 50ppm/c u1 ltm4675 4675 f34 + 32.4k 1% 50ppm/c 7.68k 1% 50ppm/c smbus interface with pmbus command set on/off control, fault management, power sequencing f swphcfg asel in r set1 13.3k r set2 1.62k out shdn adj u2 lt3060 gnd ref/byp 10.7k 1% 50ppm/c v out0 tsns 0 v orb0 + v osns0 + v osns0 ? v orb0 ? v orb1 v out1 tsns 1a tsns 1b v osns1 sgnd figure 34. 18a, 5v output dc/dc module regulator with serial interface figure 35. output derating curve of figure 34 circuit tested on dc2053, 12v in , no heat sink ambient temperature (c) 20 30 0 maximum load current (a) 2 6 8 10 18 14 40 60 4675 f35 4 16 12 80 90 100 50 70 400lfm, with u2, r set1 and r set2 installed: ja = 7.9c/w 0lfm, with u2, r set1 and r set2 installed: ja = 9.2c/w 400lfm, with u2, r set1 and r set2 not used: ja = 9.5c/w 0lfm, with u2, r set1 and r set2 not used: ja = 13c/w ltm 4675 4675f
77 for more information www.linear.com/ltm4675 appendix a similarity between pmbus, smbus and i 2 c 2-wire interface the pmbus 2-wire interface is an incremental extension of the smbus. smbus is built upon i 2 c with some minor differences in timing, dc parameters and protocol. the pmbus/smbus protocols are more robust than simple i 2 c byte commands because pmbus / smbus provide time - outs to prevent bus errors and optional packet error checking (pec) to ensure data integrity. in general, a master device that can be configured for i 2 c communication can be used for pmbus communication with little or no change to hardware or firmware. repeat start (restart) is not supported by all i 2 c controllers but is required for smbus/ pmbus reads. if a general purpose i 2 c controller is used, check that repeat start is supported. for a description of the minor extensions and exceptions pmbus makes to smbus, refer to pmbus specification part 1 revision 1.2: paragraph 5: transport. for a description of the differences between smbus and i 2 c, refer to system management bus (smbus) speci- fication version 2.0: appendix bdifferences between smbus and i 2 c. pmbus data format terminology and abbreviations used in lt c data sheets (see appendix c, for example), application notes, and the ltpowerplay gui are indicated in table 21 . table 21. data format terminology pmbus terminology meaning terminology for: specs, gui, application notes abbreviations for summary command table linear linear linear_5s_11s l11 linear (for voltage related commands) linear linear_16u l16 direct direct-manufacturer customized directmfr cf hex hex i16 ascii ascii asc register fields reg reg handshaking features are included to ensure robust system communication. please refer to the pmbus communication and command processing subsection of the applications information section for further details. ltm 4675 4675f
78 for more information www.linear.com/ltm4675 appendix b pmbus serial digital interface the ltm4675 communicates with a host ( master) using the standard pmbus serial bus interface . the timing diagram, figure 36, shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the ltm4675 is a slave device. the master can com- municate with the ltm4675 using the following formats: n master transmitter, slave receiver n master receiver, slave transmitter the following pmbus protocols are supported: n write byte, write word, send byte, block write n read byte, read word, block read n block write -- block read process call n alert response address figure 38 to figure 54 illustrate the aforementioned pmbus protocols . all transactions support pec ( parity error check ) and gcp (group command protocol). the block read supports 255 bytes of returned data. for this reason, the pmbus timeout may be extended when reading the fault log . figure 37 is a key to the protocol diagrams in this section. pec is optional. a value shown below a field in the following figures is a mandatory value for that field. the data formats implemented by pmbus are: n master transmitter transmits to slave receiver. the transfer direction in this case is not changed. n master reads slave immediately after the first byte. at the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. n combined format. during a change of direction within a transfer, the master repeats both a start condition and the slave address but with the r/w bit reversed. in this case, the master receiver terminates the transfer by generating a nack on the last byte of the transfer and a stop condition. figure 36. timing diagram sda scl t hd(sta) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf start condition stop condition repeated start condition start condition t r t f t r t f t high 4675 f36 ltm 4675 4675f
79 for more information www.linear.com/ltm4675 appendix b figure 37. pmbus packet protocol diagram element key figure 38. quick command protocol figure 39. send byte protocol figure 40. send byte protocol with pec figure 41. write byte protocol figure 42. write byte protocol with pec slave address data byte wr a a p 4675 f37 s 7 s start condition sr repeated start condition rd read (bit value of 1) wr write (bit value of 0) x shown under a field indicates that that field is required to have the value of x a acknowledge (this bit position may be 0 for an ack or 1 for a nack) p stop condition pec packet error code master to slave slave to master continuation of protocol 8 1 1 1 x x 1 1 ... slave address rd/wr a p 4675 f38 s 7 1 1 1 1 slave address command code wr a a p 4675 f39 s 7 8 1 1 1 1 1 slave address command code pec wr a a a p 4675 f40 s 7 8 8 1 1 1 1 1 1 slave address command code data byte wr a a a p 4675 f41 s 7 8 8 1 1 1 1 1 1 slave address command code data byte wr a a a p 4675 f42 s 7 8 8 1 pec 8 1 1 1 1 1 1 a ltm 4675 4675f
80 for more information www.linear.com/ltm4675 appendix b slave address command code data byte low wr a a a p 4675 f43 s 7 8 8 1 data byte high 8 1 1 1 1 1 1 a slave address command code data byte low wr a a a p 4675 f44 s 7 8 8 1 data byte high 8 pec 8 1 1 1 1 1 1 1 a a slave address command code slave address wr a a sr p 4675 f45 s 7 8 7 11 data byte 8 1 1 1 1 1 1 1 a rd na slave address command code slave address wr a a sr p 4675 f46 s 7 8 7 11 data byte 8 8 1 1 1 1 1 1 1 a rd a 1 a pec slave address command code slave address wr a a na p 4675 f47 s 7 8 7 1 data byte low 8 data byte high 8 1 1 1 1 sr 1 1 1 1 a 1 rd a slave address command code slave address wr a a a pa 4675 f48 s 7 8 7 1 data byte low 8 data byte high pec 8 8 1 1 1 1 1 11 1 sr 1 a 1 rd a slave address command code slave address wr a a sr s 7 8 7 11 byte count = n 8 1 1 1 1 1 1 a rd a ? a pna 4675 f49 data byte 1 8 data byte 2 data byte n 8 8 1 1 11 a ? slave address command code slave address wr a a sr s 7 8 7 11 byte count = n 8 1 1 1 1 1 1 a rd a ? ? a data byte 1 8 data byte 2 8 1 1 a a pna 4675 f50 data byte n pec 8 8 1 11 figure 43. write word protocol figure 44. write word protocol with pec figure 45. read byte protocol figure 46. read byte protocol with pec figure 47. read word protocol figure 48. read word protocol with pec figure 49. block read protocol figure 50. block read protocol with pec ltm 4675 4675f
81 for more information www.linear.com/ltm4675 appendix b slave address command code byte count = m wr a a s 7 8 8 1 data byte 1 8 1 1 1 1 1 a a ? ?? a data byte 2 8 1 a data byte m 8 1 slave address byte count = n rd a a sr 7 8 data byte 1 8 1 1 1 1 1 a ? p 4675 f51 1 ? ? a data byte 2 8 na data byte n 8 1 1 slave address command code byte count = m wr a a s 7 8 8 1 data byte 1 8 1 1 1 1 1 a a ? ? a data byte 2 8 1 a data byte m 8 1 slave address byte count = n rd a a sr 7 8 data byte 1 8 1 1 1 1 1 a ? ? ? a data byte 2 8 1 a data byte n 8 1 p 4675 f52 1 na pec 8 1 alert response address rd a na p 4675 f53 s 7 7 1 1 1 1 1 device address alert response address rd a a s 7 7 1 1 1 1 device address na p 4675 f54 8 1 1 pec figure 51. block write C block read process call figure 52. block write C block read process call with pec figure 53. alert response address protocol figure 54. alert response address protocol with pec ltm 4675 4675f
82 for more information www.linear.com/ltm4675 appendix c : pmbus command details addressing and write protect command name cmd code description type paged d ata format units nvm default value page 0x00 channel (page) presently selected for any paged command. r/w byte n reg 0x00 page_plus_write 0x05 write a command directly to a specified page. w block n page_plus_read 0x06 read a command directly from a specified page. block r/w process n write_protect 0x10 protect the device against unintended pmbus modifications. r/w byte n reg y 0x00 mfr_address 0xe6 specify right-justified 7-bit device address. r/w byte n reg y 0x4f mfr_rail_address 0 xfa specify unique right-justified 7-bit address for channels comprising a polyphase output. r/w byte y reg y 0x80 related commands: mfr_common. page the page command provides the ability to configure, control and monitor both pwm channels through only one physical address, either the mfr_address or global device address. each page contains the operating memory for one pwm channel. pages 0x00 and 0x01 correspond to channel 0 and channel 1, respectively, in this device. setting page to 0xff applies any following paged commands to both outputs. with page set to 0xff the ltm4675 will respond to read commands as if page were set to 0x00 (channel 0 results). this command has one data byte. page_plus_write the page_plus_write command provides a way to set the page within a device, send a command and then send the data for the command, all in one communication packet. commands allowed by the present write protection level may be sent with page_plus_write. the value stored in the page command is not affected by page_plus_write. if page_plus_ write is used to send a non-paged command, the page number byte is ignored. this command uses write block protocol. an example of the page_plus_write command with pec sending a com- mand that has two data bytes is shown in figure 55. slave address page_plus command code block count (= 4) w a a s 7 8 8 1 page number 8 1 1 1 1 1 a a ? command code 8 1 a upper data byte a a p 4675 f55 a 8 8 1 1 1 1 pec byte lower data byte 8 figure 55. example of page_plus_write ltm 4675 4675f
83 for more information www.linear.com/ltm4675 page_plus_read the page_plus_read command provides the ability to set the page within a device, send a command and then read the data returned by the command, all in one communication packet . the value stored in the page command is not affected by page_plus_read. if page_plus_read is used to access data from a non-paged command, the page number byte is ignored. this command uses block write C block read process call protocol. an example of the page_plus_read command with pec is shown in figure 56. note: page_plus commands cannot be nested. a page_plus command cannot be used to read or write another page_plus command. if this is attempted, the ltm4675 will nack the entire page_plus packet and issue a cml fault for invalid/unsupported data. write_protect the write_protect command is used to control writing to the ltm4675 device. this command does not indicate the status of the wp pin which is defined in the mfr_common command. the wp pin takes precedence over the value of this command unless the write_protect command is more stringent. byte meaning 0x80 disable all writes except to the write_protect, page, mfr_ ee_unlock and store_user_all command 0x40 disable all writes except to the write_protect, page, mfr_ee_unlock, mfr_clear_peaks, store_user_all, operation and clear_ faults command. individual fault bits can be cleared by writing a 1 to the respective bits in the status registers. 0x20 disable all writes except to the write_protect, operation, mfr_ee_unlock, mfr_clear_peaks, clear_faults, page, on_off_config, vout_command and store_user_ all. individual fault bits can be cleared by writing a 1 to the respective bits in the status registers. 0x10 reserved , must be 0 0x08 reserved , must be 0 0x04 reserved , must be 0 0x02 reserved , must be 0 0x01 reserved , must be 0 enable writes to all commands when write_protect is set to 0x00. this command has one data byte. appendix c : pmbus command details figure 56. example of page_plus_read p 1 slave address page_plus command code block count (= 2) w a a s 7 8 8 1 page number 8 1 1 1 1 1 a a ? command code 8 1 a slave address block count (= 2) lower data byte r a a sr 7 8 8 1 upper data byte 8 1 1 1 1 1 a a pec byte 8 1 na 4676a f56 ltm 4675 4675f
84 for more information www.linear.com/ltm4675 if wp pin is high, page, operation, mfr_clear_peaks, mfr_ee_unlock and clear_ faults commands are supported. individual fault bits can be cleared by writing a 1 to the respective bits in the status registers. mfr_address the mfr_address command byte sets the 7 bits of the pmbus slave address for this device. setting this command to a value of 0x80 disables device addressing. the global device address, 0x5a and 0x5b, cannot be deactivated. if rconfig is set to ignore (mfr_config_all[6]=1 b ), the asel pin is still used to determine the lsb of the channel address. if the asel pin is open, the ltm4675 will use the four lsbs of the mfr_address stored in eeprom. values of 0x5a, 0x5b, 0x0c, and 0x7c are not recommended. this command has one data byte. mfr_rail_address the mfr_rail_address command enables direct device address access to the page activated channel. the value of this command should be common to all devices attached to a single power supply rail. the user should only perform command writes to this address. if a read is performed from this address and the rail devices do not respond with exactly the same value, the ltm4675 will detect bus contention and set a cml com- munications fault. setting this command to a value of 0x80 disables rail device addressing for the channel. this command has one data byte. general configuration registers command name cmd code description type paged d ata format units nvm default value mfr_chan_config 0xd0 configuration bits that are channel specific. r/w byte y reg y 0x1f mfr_config_all 0xd1 configuration bits that are common to all pages. r/w byte n reg y 0x09 mfr_chan_config general purpose configuration command common to multiple lt c products. bit meaning 7 reserved 6 reserved 5 reserved 4 disable run low. when asserted the run pin is not pulsed low if commanded off 3 short cycle. when asserted the output will immediate off if commanded on while waiting for toff_delay or toff_fall. toff_min of 120ms is honored then the part will command on. 2 share_clock control, if share_clock is held low, the output is disabled 1 no gpio alert, alert is not pulled low if gpio is pulled low externally. assert this bit if either power_good or vout_uvuf are propagated on gpio 0 disables the vout decay value requirement for mfr_ retry_ time processing. when this bit is set to a 0, the output must decay to less than 12.5% of the programmed value for any action that turns off the rail including a fault, an off/ on command, or a toggle of run from high to low to high. this command has one data byte. appendix c : pmbus command details ltm 4675 4675f
85 for more information www.linear.com/ltm4675 appendix c : pmbus command details mfr_config_all general purpose configuration command common to multiple lt c products bit meaning 7 enable fault logging 6 ignore resistor configuration pins 5 disable cml fault for quick command message 4 disable sync out 3 enable 255ms time out 2 a valid pec required for pmbus writes to be accepted. if this bit is not set, the part will accept commands with invalid pec. 1 enable the use of pmbus clock stretching 0 enables a low to high transition on either run pin to issue a clear_ faults command this command has one data byte. on/off/margin command name cmd code description type paged d ata format units nvm default value on_off_config 0x02 run pin and pmbus bus on/off command configuration. r/w byte y reg y 0x1f operation 0x01 operating mode control. on/off, margin high and margin low. r/w byte y reg y 0x80 mfr_reset 0xfd commanded reset without requiring a power-down. identical to restore_user_all. send byte n na on_off_config the on_off _config command configures the combination of run n pin input and serial bus commands needed to turn the unit on and off. this includes how the unit responds when power is applied. the only bits allowed to be changed are as follows: 3: controls how the unit responds to commands received via the serial bus 0: run pin action when commanding the unit to turn off. if bit 0 is set to one, the part will stop transferring power to the output stage as fast as possible. this will have the effect of the load discharging the output capacitor. setting bit 0 to a zero will cause the regulator to use the programmed turn-off delay and fall times. if the part is in continu- ous mode, the programmed turn-off response may pull the output to zero volts considerably faster than removing power immediately from the load. changing the value of bits 4, 2 or 1, will generate a cml fault. this command has one data byte. ltm 4675 4675f
86 for more information www.linear.com/ltm4675 appendix c : pmbus command details operation the operation command is used to turn the unit on and off in conjunction with the input from the run n pins. it is also used to cause the unit to set the output voltage to the upper or lower margin voltages. the unit stays in the commanded operating mode until a subsequent operation command or change in the state of the run n pin instructs the device to change to another mode. if the part is stored in the margin_low/high state, the next mfr_reset or restore_user_all or sv in power cycle will ramp to that state. if the operation command is modified, for example on is changed to margin_low, the output will move at a fixed slope set by the vout_transition_ rate . the default operation command is sequence off. margin high (ignore faults) and margin low (ignore faults) operations are not supported by the ltm4675. the part defaults to the sequence off state. this command has one data byte. table 22. on_off_config detailed register information on_off_config data contents bits( s ) symbol operation b[7:5] reserved dont care. always returns 0. b[3] on_off_config_use_pmbus controls how the unit responds to commands received via the serial bus. 0: unit ignores the operation command b[7:6]. 1: unit responds to operation command b[7:6]. the unit also requires the runn pin to be asserted for the unit to start. b[0] on_off_config_control_fast_off runn pin turn off action when commanding the unit to turn off. 0: use the programmed toff_ delay. 1: turn off the output and stop transferring energy as quickly as possible. the device does not sink current in order to decrease the output voltage fall time. note: a high on the run pin is always required to start power conversion. power conversion will always stop with a low on run. table 23. operation command detail register operation data contents when on_off_config_use_pmbus enables operation_control symbol action value bits function turn off immediately 0x00 turn on 0x80 margin low 0x98 margin high 0xa8 sequence off 0x40 operation data contents when on_off_config is configured such that operation command is not used to command channel on or off symbol action value bits function output at nominal 0x80 margin low 0x98 margin high 0xa8 note: attempts to write a reserved value will cause a cml fault. ltm 4675 4675f
87 for more information www.linear.com/ltm4675 appendix c : pmbus command details mfr_reset this command provides a means by which the user can perform a reset of the ltm4675. identical to restore_ user_ all. this write-only command has no data bytes. pwm config command name cmd code description type paged d ata format units nvm default value mfr_pwm_mode 0xd4 configuration for the pwm engine of each channel. r/w byte y reg y 0xc1 mfr_pwm_config 0xf5 set numerous parameters for the dc/dc controller including phasing. r/w byte n reg y 0x10 frequency_switch 0x33 switching frequency of the controller. r/w word n l11 khz y 500 0xfbe8 mfr_pwm_mode the mfr_pwm_mode command allows the user to program the pwm controller to use, discontinuous (pulse-skipping mode), or forced continuous conduction mode. bit meaning 7 range of i limit 0 C low current range 1 C high current range 6 enable servo mode 5 reserved 4 page 0 only: use of tsns 1a -sensed temperature telemetry 0 - temperature sensed via tsns 1a is used to temperature-correct the current-sense information digitized by channel 1. 1 - temperature sensed via tsns 0 is used to temperature-correct the current-sense information digitized by channel 1. telemetry obtained from the thermal sensor connected to tsns 1 a can be external to the module, if desired. 3 reserved 2 reserved 1 voltage range 0 - hi voltage range 5.5 volts max 1 - lo voltage range 2.75 volts max 0 pwm mode 0 - discontinuous mode 1 - continuous mode whenever the channel is ramping on, the pwm mode will be discontinuous, regardless of the value of this command. bit [7] of this command determines if the part is in high range or low range of the iout_oc _fault_limit command. changing this bit value changes the pwm loop gain and compensation. changing this bit value whenever an output is active may have detrimental system results. ltm 4675 4675f
88 for more information www.linear.com/ltm4675 appendix c : pmbus command details bit [6] the ltm4675 will not servo while the part is off, ramping on or ramping off. when set to a one, the output servo is enabled. the output set point dac will be slowly adjusted to minimize the difference between the read_vout_adc and the vout_command (or the appropriate margined value). bit [1] of this command determines if the part is in high range or low voltage range. changing this bit value changes the pwm loop gain and compensation. this bit value cannot be changed when an output is active. this command has one data byte. mfr_pwm_config the mfr_pwm_config command sets the switching frequency phase offset with respect to the falling edge of the sync signal. the part must be in the off state to process this command. either the run pins must be low or the part must be commanded off. if the part is in the run state and this command is written, the command will be ignored and a busy fault will be asserted. bit 7 allows remote differential voltage sensing for polyphase rail applications. bit meaning 7 ea connection 0 C independent ea and channel outputs 1 C ea1 uses ea0 input for polyphase operation 6 reserved . 5 reserved 4 share clock enable : if this bit is 1, the share_clk pin will not be released until sv in > vin_on. the share_clk pin will be pulled low when sv in < vin_off. if this bit is 0, the share_clk pin will not be pulled low when sv in < vin_off except for the initial application of sv in . 3 reserved bit [2:0] channel 0 (degrees) channel 1 (degrees) 000b 0 180 001b 90 270 010b 0 240 011b 0 120 100b 120 240 101b 60 240 110b 120 300 do not assert bit [7] unless it is a polyphase application and both v out pins are tied together and both comp n a pins are tied together. this command has one data byte. ltm 4675 4675f
89 for more information www.linear.com/ltm4675 appendix c : pmbus command details frequency_switch the frequency_switch command sets the switching frequency, in khz, of a pmbus device. see table 7 for recom- mended values. supported frequencies: value [15:0] resulting frequency ( typ ) 0x0000 external oscillator 0xf3e8 250khz 0 xfabc 350khz 0xfb52 425khz 0xfbe8 500khz 0x023f 575khz 0x028a 650khz 0x02ee 750khz 0x03e8 1000khz the part must be in the off state to process this command. either the run pins must be low or the part must be commanded off. if the part is in the run state and this command is written, the command will be ignored and a busy fault will be asserted. when the part is commanded off and the frequency is changed, a pll_unlock status may be detected as the pll locks onto the new frequency. this command has two data bytes and is formatted in linear_5s_11s format. voltage input voltage (sv in ) and limits command name cmd code description type paged d ata format units nvm default value vin_ov_fault_ limit 0x55 input supply (sv in ) overvoltage fault limit. r/w word n l11 v y 17.44 0xda2e vin_uv_warn_limit 0x58 input supply (sv in ) undervoltage warning limit. r/w word n l11 v y 5.297 0xcaa6 vin_on 0x35 input voltage (sv in ) at which the unit should start power conversion. r/w word n l11 v y 5.500 0xcac0 vin_off 0x36 input voltage (sv in ) at which the unit should stop power conversion. r/w word n l11 v y 5.250 0xcaa0 vin_ov_fault_limit the vin_ov_fault_limit command sets the value of the measured (sv in ) input voltage, in volts, that causes an input overvoltage fault. the fault is detected with the a/d converter resulting in latency up to 100ms, typical . this command has two data bytes and is formatted in linear_5s_11s format. vin_uv_warn_limit the vin_uv_warn_limit command sets the value of the sv in input voltage that causes an sv in input undervoltage warning. the warning is detected with the a/d converter resulting in latency up to 100ms, typical. this command has two data bytes and is formatted in linear _5s_11s format. ltm 4675 4675f
90 for more information www.linear.com/ltm4675 appendix c : pmbus command details vin_on the vin_on command sets the sv in input voltage, in volts, at which the unit should start power conversion. this command has two data bytes and is formatted in linear_5s_11s format. vin_off the vin_off command sets the sv in input voltage, in volts, at which the unit should stop power conversion. this command has two data bytes and is formatted in linear_5s_11s format. output voltage and limits command name cmd code description type paged d ata format units nvm default value vout_mode 0x20 output voltage format and exponent (2 C12 ). r byte y reg 2 C12 0x14 vout_max 0x24 upper limit on the commanded output voltage including vout_margin_high. r/w word y l16 v y 5.6 0x599a vout_ov_fault_ limit 0x40 output overvoltage fault limit. r/w word y l16 v y 1.1 0x119a vout_ov_warn_ limit 0x 42 output overvoltage warning limit. r/w word y l16 v y 1.075 0x1133 vout_margin_high 0x25 margin high output voltage set point. must be greater than vout_command. r/w word y l16 v y 1.05 0x10cd vout_command 0x21 nominal output voltage set point. r/w word y l16 v y 1.0 0x1000 vout_margin_low 0x26 margin low output voltage set point. must be less than vout_command. r/ w word y l16 v y 0.95 0x0f33 vout_uv_warn_ limit 0x43 output undervoltage warning limit. r/w word y l16 v y 0.925 0x0ecd vout_uv_fault_ limit 0x44 output undervoltage fault limit. r/w word y l16 v y 0.9 0x0e66 mfr_vout_max 0xa5 maximum allowed output voltage including vout_ov_fault_limit. r word y l16 v 5.7 0x5b34 vout_mode the data byte for vout_mode command, used for commanding and reading output voltage, consists of a 3-bit mode (only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage read/write commands. this read-only command has one data byte. vout_max the vout_max command sets an upper limit on any voltage, including vout_margin_high, the unit can command regardless of any other commands or combinations. the maximum allowed value of this command is 5.7 volts. the maximum output voltage the ltm4675 can produce is 5.5 volts including vout_margin_high . however, the vout_ov_fault_limit can be commanded as high as 5.7 volts. this command has two data bytes and is formatted in linear_16u format. ltm 4675 4675f
91 for more information www.linear.com/ltm4675 appendix c : pmbus command details vout_ov_fault_limit the vout_ov_fault_limit command sets the value of the output voltage measured at the sense pins, in volts, which causes an output overvoltage fault. if the vout_ov_fault_limit is modified and the switcher is active, allow 10ms after the command is modified to assure the new value is being honored. the part indicates if it is busy making a calculation. monitor bits 5 and 6 of mfr_common. either bit is low if the part is busy. if this wait time is not met, and the vout_command is modified above the old overvoltage limit, an ov condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher. if vout_ov_fault_response is set to ov_pulldown, the gpio pin will not assert if vout_ov_ fault is propa- gated. the ltm4675 will pull the tg low and assert the bg bit as soon as the overvoltage condition is detected. this command has two data bytes and is formatted in linear_16u format. vout_ov_warn_limit the vout_ov_warn_limit command sets the value of the output voltage measured at the sense pins , in volts, which causes an output voltage high warning. the read_vout value will be used to determine if this limit has been exceeded. in response to the vout_ov_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_ byte ? sets the vout bit in the status_word ? sets the vout overvoltage warning bit in the status_vout command ? notifies the host by asserting alert pin, unless masked. this condition is detected by the adc so the response time may be up to 100ms, typical. this command has two data bytes and is formatted in linear_16u format. vout_margin_high the vout_margin_high command loads the unit with the voltage to which the output is to be changed, in volts, when the operation command is set to margin high. the value must be greater than vout_command. the maximum guaranteed value on vout_margin_high is 5.5 volts. this command will not be acted on during ton _ rise and toff _ fall output sequencing . the vout _ transition _ rate will be used if this command is modified while the output is active and in a steady-state condition. this command has two data bytes and is formatted in linear_16u format. vout_command the vout_command consists of two bytes and is used to set the output voltage, in volts. the maximum guaranteed value on vout is 5.5 volts. this command will not be acted on during ton _ rise and toff _ fall output sequencing . the vout _ transition _ rate will be used if this command is modified while the output is active and in a steady-state condition. this command has two data bytes and is formatted in linear_16u format. ltm 4675 4675f
92 for more information www.linear.com/ltm4675 appendix c : pmbus command details vout_margin_low the vout_margin_low command loads the unit with the voltage to which the output is to be changed, in volts, when the operation command is set to margin low. the value must be less than vout_command. this command will not be acted on during ton _ rise and toff _ fall output sequencing . the vout _ transition _ rate will be used if this command is modified while the output is active and in a steady-state condition. this command has two data bytes and is formatted in linear_16u format. vout_uv_warn_limit the vout_uv_ warn_limit command reads the value of the output voltage measured at the sense pins, in volts, which causes an output voltage low warning. in response to the vout_uv_ warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_ byte ? sets the vout bit in the status_word ? sets the vout undervoltage warning bit in the status_vout command ? notifies the host by asserting alert pin, unless masked. this condition is detected by the adc so the response time may be up to 100ms, typical. this command has two data bytes and is formatted in linear_16u format. vout_uv_fault_limit the vout_uv_fault_limit command reads the value of the output voltage measured at the sense pins, in volts, which causes an output undervoltage fault. this command has two data bytes and is formatted in linear_16u format. mfr_vout_max the mfr_vout_max command is the maximum output voltage in volts for each channel including vout_ov_fault_ limit. if the output voltages are set to high range (bit 1 of mfr_pwm_mode set to a 0) mfr_vout_max for channel 0 and 1 is 5.7v. if the output voltages are set to low range (bit 1 of mfr_pwm_mode set to a 1) the mfr_vout_max for both channels is 2.75v. entering vout_command values greater than this will result in a cml fault and the output voltage setting will be clamped to the maximum level. this read-only command has 2 data bytes and is formatted in linear_16u format. current input current calibration command name cmd code description type paged d ata format units nvm default value mfr_iin_offset 0xe9 coefficient used to add to the input current to account for the iq of the part. r/w word y l11 a y 0.02956 0x8bc9 ltm 4675 4675f
93 for more information www.linear.com/ltm4675 appendix c : pmbus command details mfr_iin_offset the mfr_iin_offset command allows the user to set an input current representing the quiescent current of each channel. for accurate results at low output current, the part should be in continuous conduction mode. (mfr_pwm_ mode[0]=1 b ). see table 8 for recommended values. this command has 2 data bytes and is formatted in linear_5s_11s format. output current calibration command name cmd code description type paged d ata format units nvm default value iout_cal_gain 0x38 the ratio of the voltage at the current sense pins to the sensed current. r/w word y l11 m factory - only nvm trimmed , 4.46m? typical mfr_iout_cal_gain_tc 0xf6 temperature coefficient of the current sensing element. r/w word y cf y 3860 0x0f14 iout_cal_gain the iout_cal_gain command is nominally used to set the resistance value of the current sense element, in milliohms. (see also mfr_iout_cal_gain_tc). writes to this register result in a nack and do not impact output current read- back telemetry. this command has two data bytes and is formatted in linear_5s_11s format. mfr_iout_cal_gain_tc the mfr_ iout_ cal_ gain_ tc command allows the user to program the temperature coefficient of the iout_ cal_ gain inductor dcr in ppm/c. this command has two data bytes and is formatted in 16-bit 2s complement integer ppm. n = C32768 to 32767 ? 10 C6 . nominal temperature is 27c. the iout_cal_gain is multiplied by: [1.0 + mfr_iout_cal_gain_tc ? (read_temperature_ 1 - 27)]. dcr sensing will have a typical value of 3900. the iout_cal_gain and mfr_iout_cal_gain_tc impact all current parameters including: read_iout, read_iin, iout_oc_fault_limit and iout_oc_warn_limit. writes to this register are not recommended; use the factory- default value. input current command name cmd code description type paged d ata format units nvm default value iin_oc_warn_limit 0x5d input overcurrent warning limit. r/w word n l11 a y 8.5 0xd220 iin_oc_warn_limit the iin_oc_warn_limit command sets the value of the input current, in amperes, that causes a warning indicating the input current is high. the read_iin value will be used to determine if this limit has been exceeded. in response to the iin_oc_warn_limit being exceeded, the device: ? sets the other bit in the status_ byte ? sets the input bit in the upper byte of the status_word ltm 4675 4675f
94 for more information www.linear.com/ltm4675 appendix c : pmbus command details ? sets the iin overcurrent warning bit in the status_input command, and ? notifies the host by asserting alert pin, unless masked this condition is detected by the adc so the response time may be up to 100ms, typical. this command has two data bytes and is formatted in linear_5s_11s format. output current command name cmd code description type paged d ata format units nvm default value iout_oc_fault_limit 0x46 output overcurrent fault limit. r/w word y l11 a y 15.80 0xd3f3 iout_oc_warn_limit 0x4a output overcurrent warning limit. r/w word y l11 a y 10.80 0xd2b3 iout_oc_fault_limit the iout_oc_fault_limit command sets the value of the peak output current limit, in amperes. when the controller is in current limit, the overcurrent detector will indicate an overcurrent fault condition. the programmed overcurrent fault limit value is rounded up to the nearest one of the following set of discrete values: 25mv/iout_cal_gain low range (1.5x nominal loop gain) mfr_pwm_mode [7]=0 28.6mv/iout_cal_gain 32.1mv/iout_cal_gain 35.7mv/iout_cal_gain 39.3mv/iout_cal_gain 42.9mv/iout_cal_gain 46.4mv/iout_cal_gain 50mv/iout_cal_gain 37.5mv/iout_cal_gain high range (nominal loop gain) mfr_pwm_mode [7]=1 42.9mv/iout_cal_gain 48.2mv/iout_cal_gain 53.6mv/iout_cal_gain 58.9mv/iout _cal_gain 64.3mv/iout_cal_gain 69.6mv/iout_cal_gain 75mv/iout_cal_gain note: this is the peak of the current waveform. the read_iout command returns the average current. the peak output current limits are adjusted with temperature based on the mfr_iout_cal_gain_tc using the equation: iout_oc_fault_limit = iout_cal_gain ? (1 + mfr_iout_cal_gain_tc ? (read_temperture_1-27.0)). the ltpowerplay gui automatically convert the voltages to currents. the i out range is set with bit 7 of the mfr_pwm_mode command. the iout_oc_fault_limit is ignored during ton_rise and toff_ fall. this command has two data bytes and is formatted in linear_5s_11s format. ltm 4675 4675f
95 for more information www.linear.com/ltm4675 appendix c : pmbus command details iout_oc_warn_limit this command sets the value of the output current that causes an output overcurrent warning in amperes. the read_iout value will be used to determine if this limit has been exceeded. in response to the iout_oc_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_ byte ? sets the iout bit in the status_word ? sets the iout overcurrent warning bit in the status_iout command, and ? notifies the host by asserting alert pin, unless masked. this condition is detected by the adc so the response time may be up to 100ms, typical. the iout_oc_fault_limit is ignored during ton_rise and toff_ fall. this command has two data bytes and is formatted in linear _5s_11s format temperature power stage dcr temperature calibration command name cmd code description type paged d ata format units nvm default value mfr_temp_1_gain 0xf8 sets the slope of the power stage temperature sensor. r/w word y cf y 0.995 0x3 fae mfr_temp_1_offset 0xf9 sets the offset of the power stage temperature sensor with respect to C273.1c. r/w word y l11 c y 0 0x8000 mfr_temp_1_gain the mfr_temp_1_gain command will modify the slope of the power stage temperature sensor to account for non- idealities in the element and errors associated with the remote sensing of the temperature in the inductor. this command has two data bytes and is formatted in 16-bit 2s complement integer. n = 8192 to 32767. the effective adjustment is n ? 2 C14 . the nominal value is 1. mfr_temp_1_offset the mfr_temp_1_offset command will modify the offset of the power stage temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor. this command has two data bytes and is formatted in linear_5s_11s format. the part starts the calculation with a value of C273.15 so the default adjustment value is zero. ltm 4675 4675f
96 for more information www.linear.com/ltm4675 appendix c : pmbus command details power stage temperature limits command name cmd code description type paged d ata format units nvm default value ot_fault_limit 0x4f power stage overtemperature fault limit. r/w word y l11 c y 128 0xf200 ot_warn_limit 0x51 power stage overtemperature warning limit. r/w word y l11 c y 125 0xebe8 ut_fault_limit 0x53 power stage undertemperature fault limit. r/w word y l11 c y C45 0xe530 ot_fault_limit the ot_fault_limit command sets the value of the power stage temperature, in degrees celsius, which causes an overtemperature fault. the read_temperature_1 value will be used to determine if this limit has been exceeded. this condition is detected by the adc so the response time may be up to 100ms, typical. this command has two data bytes and is formatted in linear_5s_11s format. ot_warn_limit the ot_ warn_limit command sets the value of the power stage temperature, in degrees celsius, which causes an overtemperature warning. the read_temperature_1 value will be used to determine if this limit has been exceeded. in response to the ot_warn_limit being exceeded, the device: ? sets the temperature bit in the status_ byte ? sets the overtemperature warning bit in the status_ temperature command, and ? notifies the host by asserting alert pin, unless masked. this condition is detected by the adc so the response time may be up to 100ms, typical. this command has two data bytes and is formatted in linear_5s_11s format. ut_fault_limit the ut_fault_limit command sets the value of the power stage temperature, in degrees celsius, which causes an undertemperature fault. the read_temperature_1 value will be used to determine if this limit has been exceeded. this condition is detected by the adc so the response time may be up to 100ms, typical. this command has two data bytes and is formatted in linear_5s_11s format. ltm 4675 4675f
97 for more information www.linear.com/ltm4675 appendix c : pmbus command details timing timing on sequence/ramp command name cmd code description type paged d ata format units nvm default value ton_ delay 0x60 time from run and/or operation on to output rail turn-on. r/w word y l11 ms y 0.0 0x8000 ton_rise 0x61 time from when the output starts to rise until the output voltage reaches the vout commanded value. r/w word y l11 ms y 3.0 0xc300 ton_max_fault_limit 0x62 maximum time from the start of ton_rise for vout to cross the vout_uv_fault_limit. r/w word y l11 ms y 5.0 0xca80 vout_transition_ rate 0x27 rate the output changes when vout commanded to a new value. r/w word y l11 v/ms y 0.001 0x8042 ton_ delay the ton_ delay command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. values from 0ms to 83 seconds are valid. this command has two data bytes and is formatted in linear_5s_11s format. ton_rise the ton_rise command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. values from 0 to 1.3 seconds are valid. the part will be in discontinuous mode during ton_rise events . if ton_rise is less than 0.25ms, the ltm4675 digital slope will be bypassed. the output voltage transition will be controlled by the analog performance of the pwm switcher. the maximum allowed slope is 4v/ms. this command has two data bytes and is formatted in linear_5s_11s format. ton_max_fault_limit the ton_max_fault_limit command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. a data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. the maximum limit is 83 seconds. this command has two data bytes and is formatted in linear_5s_11s format. vout_transition_ rate when a pmbus device receives either a vout_command or operation (margin high, margin low) that causes the output voltage to change this command set the rate in v/ms at which the output voltage changes. this commanded rate of change does not apply when the unit is commanded on or off. this command has two data bytes and is formatted in linear_5s_11s format. ltm 4675 4675f
98 for more information www.linear.com/ltm4675 appendix c : pmbus command details timing off sequence/ramp command name cmd code description type paged d ata format units nvm default value toff_ delay 0x64 time from run and/or operation off to the start of toff_ fall ramp. r/w word y l11 ms y 0.0 0x8000 toff_ fall 0x65 time from when the output starts to fall until the output reaches zero volts. r/w word y l11 ms y 3.0 0xc300 toff_max_warn_limit 0x66 maximum allowed time, after toff _ fall completed, for the unit to decay below 12.5%. r/w word y l11 ms y 0.0 0x8000 toff_ delay the toff_ delay command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. values from 0 to 83 seconds are valid. this command is excluded from fault events. this command has two data bytes and is formatted in linear_5s_11s format. toff_ fall the toff_ fall command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt- age is commanded to zero. it is the ramp time of the v out dac. when the v out dac is zero, the part will three-state. the part will maintain the mode of operation programmed. for defined toff_ fall times, the user should set the part to continuous conduction mode. loading the max value indicates the part will ramp down at the slowest possible rate. the minimum supported fall time is 0.25ms. a value less than 0.25ms will result in a 0.25ms ramp. the maximum fall time is 1.3 seconds. the maximum allowed slope is 4v/ms. in discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. this command has two data bytes and is formatted in linear_5s_11s format. toff_max_warn_limit the toff_max_warn_limit command sets the value, in milliseconds, on how long the unit can attempt to turn off the output until a warning is asserted. the output is considered off when the v out voltage is less than 12.5% of the programmed vout_command value. the calculation begins after toff_fall is complete. toff_max_warn is not enabled in vout_ decay is disabled. a data value of 0ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely. other than 0, values from 120ms to 524 seconds are valid. this command has two data bytes and is formatted in linear_5s_11s format. precondition for restart command name cmd code description type paged d ata format units nvm default value mfr_restart_ delay 0xdc delay from actual run active edge to virtual run active edge. r/w word y l11 ms y 150 0xf258 ltm 4675 4675f
99 for more information www.linear.com/ltm4675 appendix c : pmbus command details mfr_restart_ delay this command specifies the minimum run off time in milliseconds. this device will pull the run pin low for this length of time once a falling edge of run has been detected. the minimum recommended value is 136ms. note: the restart delay is different than the retry delay. the restart delay pulls run low for the specified time, after which a standard start-up sequence is initiated. the minimum restart delay should be equal to toff_delay + toff_fall + 136ms. valid values are from 136ms to 65.52 seconds in 16ms increments. to assure a minimum off time, set the mfr_restart_delay 16ms longer than the desired time. the output rail can be off longer than the mfr_ restart_delay after the run pin is pulled high if the output decay bit 1 is enabled in mfr_chan_config and the output takes a long time to decay below 12.5% of the programmed value. this command has two data bytes and is formatted in linear_5s_11s format. fault response fault responses all faults command name cmd code description type paged d ata format units nvm default value mfr_retry_ delay 0xdb retry interval during fault retry mode. r/w word y l11 ms y 250 0xf3e8 mfr_retry_ delay this command sets the time in milliseconds between restarts if the fault response is to retry the controller at specified intervals . this command value is used for all fault responses that require retry . the retry time starts once the fault has been detected by the offending channel. valid values are from 120ms to 83.88 seconds in 10s increments. note: the retry delay time is determined by the longer of the mfr_retry_delay command or the time required for the regulated output to decay below 12.5% of the programmed value. if the natural decay time of the output is too long, it is possible to remove the voltage requirement of the mfr_retry_delay command by asserting bit 0 of mfr_chan_config. this command has two data bytes and is formatted in linear_5s_11s format. fault responses input voltage (sv in ) command name cmd code description type paged d ata format units nvm default value vin_ov_fault_response 0x56 action to be taken by the device when an sv in input supply overvoltage fault is detected. r/w byte y reg y 0xb8 vin_ov_fault_response the vin_ov_fault_response command instructs the device on what action to take in response to an (sv in ) input overvoltage fault. the data byte is in the format given in table 28. the device also: ? sets the none_of_the_above bit in the status_ byte ? set the input bit in the upper byte of the status_word ltm 4675 4675f
100 for more information www.linear.com/ltm4675 appendix c : pmbus command details ? sets the sv in overvoltage fault bit in the status_input command, and ? notifies the host by asserting alert pin, unless masked. this command has one data byte. fault responses output voltage command name cmd code description type paged d ata format units nvm default value vout_ov_fault_response 0x41 action to be taken by the device when an output overvoltage fault is detected. r/w byte y reg y 0x7a vout_uv_fault_response 0x45 action to be taken by the device when an output undervoltage fault is detected. r/w byte y reg y 0xb8 ton_max_fault_ response 0x63 action to be taken by the device when a ton_max_ fault event is detected. r/w byte y reg y 0xb8 vout_ov_fault_response the vout_ov_fault_response command instructs the device on what action to take in response to an output overvoltage fault. the data byte is in the format given in table 24. the device also: ? sets the vout_ov bit in the status_ byte ? sets the vout bit in the status_word ? sets the vout overvoltage fault bit in the status_vout command ? notifies the host by asserting alert pin, unless masked. the only value recognized for this command are: 0x80Cthe device shuts down (disables the output) and the unit does not attempt to retry . the output remains disabled until the fault is cleared (pmbus, part ii, section 10.7). 0xb8Cthe device shuts down (disables the output) and device attempts retry continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. 0x4n the device shuts down and the unit does not attempt to retry. the output remains disabled until the part is commanded off then on or the run pin is asserted low then high or mfr_reset or restore_user_all through the command or removal of sv in . the ov fault must remain active for a period of n ? 10s, where n is a value from 0 to 7. 0x78+n the device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded off then on or the run pin is asserted low then high or mfr_reset or restore_user_all through the command or removal of sv in . the ov fault must remain active for a period of n ? 10s, where n is a value from 0 to 7. any other value will result in a cml fault and the write will be ignored. this command has one data byte. ltm 4675 4675f
101 for more information www.linear.com/ltm4675 appendix c : pmbus command details vout_uv_fault_response the vout_uv_fault_response command instructs the device on what action to take in response to an output undervoltage fault. the data byte is in the format given in table 25. the device also: ? sets the vout bit in the status_word ? sets the vout undervoltage fault bit in the status_vout command ? notifies the host by asserting alert pin, unless masked. the uv fault and warn are masked until the following criteria are achieved: 1) the ton_max_fault_limit has been reached 2) the ton_ delay sequence has completed 3) the ton_rise sequence has completed 4) the vout_uv_fault_limit threshold has been reached 5) the iout_oc_fault_limit is not present the uv fault and warn are masked whenever the channel is not active. the uv fault and warn are masked during ton_rise and toff_ fall sequencing. this command has one data byte. table 24. vout_ov_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltm4675: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_ faults command. ? the output is commanded through the runn pin, the operation command, or the combined action of the runn pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltm4675. 00 part performs ov pull down only (i.e., turns off the top mosfet and turns on lower mosfet while v out is > vout_ov_ fault) 01 the pmbus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. if the fault condition is still present at the end of the delay time, the unit responds as programmed in the retry setting (bits [5:3]). 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000-110 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off (by the runn pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_retry_ delay command. 2:0 delay time xxx the delay time in 10s increments. this delay time determines how long the controller continues operating after a fault is detected. only valid for deglitched off state ltm 4675 4675f
102 for more information www.linear.com/ltm4675 appendix c : pmbus command details ton_max_fault_response the ton_max_fault_response command instructs the device on what action to take in response to a ton_max fault. the data byte is in the format given in table 28. the device also: ? sets the none_of_the_above bit in the status_ byte ? sets the vout bit in the status_word ? sets the ton_max_ fault bit in the status_vout command, and ? notifies the host by asserting alert pin, unless masked. ? a value of 0 disables the ton_max_fault_response. it is not recommended to use 0. this command has one data byte. table 25. vout_uv_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltm4675: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_ faults command ? the output is commanded through the runn pin, the operation command, or the combined action of the runn pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltm4675 00 the pmbus device continues operation without interruption. (ignores the fault functionally) 01 the pmbus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. if the fault condition is still present at the end of the delay time, the unit responds as programmed in the retry setting (bits [5:3]). 10 the device shuts down (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000-110 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off (by the runn pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_retry_ delay command. 2:0 delay time xxx the delay time in 10s increments. this delay time determines how long the controller continues operating after a fault is detected. only valid for deglitched off state. ltm 4675 4675f
103 for more information www.linear.com/ltm4675 appendix c : pmbus command details fault responses output current command name cmd code description type paged d ata format units nvm default value iout_oc_fault_response 0x47 action to be taken by the device when an output overcurrent fault is detected. r/w byte y reg y 0x00 iout_oc_fault_response the iout_oc_fault_response command instructs the device on what action to take in response to an output overcurrent fault. the data byte is in the format given in table 26. the device also: ? sets the iout_oc bit in the status_ byte ? sets the iout bit in the status_word ? sets the iout overcurrent fault bit in the status_iout command, and ? notifies the host by asserting alert pin, unless masked. this command has one data byte. table 26. iout_oc_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltm4675: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_ faults command ? the output is commanded through the runn pin, the operation command, or the combined action of the runn pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltm4675. 00 the ltm4675 continues to operate indefinitely while maintaining the output current at the value set by iout_oc_ fault_limit without regard to the output voltage (known as constant- current or brick-wall limiting). 01 not supported. 10 the ltm4675 continues to operate, maintaining the output current at the value set by iout_oc_fault_limit without regard to the output voltage, for the delay time set by bits [2:0]. if the device is still operating in current limit at the end of the delay time, the device responds as programmed by the retry setting in bits [5:3]. 11 the ltm4675 shuts down immediately and responds as programmed by the retry setting in bits [5:3]. 5:3 retry setting 000-110 the unit does not attempt to restart. the output remains disabled until the fault is cleared by cycling the runn pin or removing bias power. 111 the device attempts to restart continuously, without limitation, until it is commanded off (by the runn pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. note: the retry interval is set by the mfr_retry_ delay command. 2:0 delay time xxx the number of delay time units in 16ms increments. this delay time is used to determine the amount of time a unit is to continue operating after a fault is detected before shutting down. only valid for deglitched off state. ltm 4675 4675f
104 for more information www.linear.com/ltm4675 appendix c : pmbus command details fault responses ic temperature command name cmd code description type paged d ata format units nvm default value mfr_ot_fault_ response 0xd6 action to be taken by the device when an internal overtemperature fault is detected. r byte n reg 0xc0 mfr_ot_fault_response the mfr_ot_fault_response command byte instructs the device on what action to take in response to an internal overtemperature fault. the data byte is in the format given in table 27 . the ltm4675 also: ? sets the mfr bit in the status_word, and ? sets the overtemperature fault bit in the status_mfr_specific command ? notifies the host by asserting alert pin, unless masked. this command has one data byte. table 27. data byte contents mfr_ot_fault_response bits description value meaning 7:6 response for all values of bits [7:6], the ltm4675: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_ faults command ? the output is commanded through the runn pin, the operation command, or the combined action of the runn pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltm4675 00 not supported. writing this value will generate a cml fault. 01 not supported. writing this value will generate a cml fault 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 the devices output is disabled while the fault is present. operation resumes and the output is enabled when the fault condition no longer exists. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared. 001-111 not supported. writing this value will generate cml fault. 2:0 delay time xxx not supported. value ignored fault responses power stage temperature command name cmd code description type paged d ata format units nvm default value ot_fault_ response 0x50 action to be taken by the device when a power stage overtemperature fault is detected, r/w byte y reg y 0xb8 ut_fault_ response 0x54 action to be taken by the device when a power stage undertemperature fault is detected. r/w byte y reg y 0x00 ltm 4675 4675f
105 for more information www.linear.com/ltm4675 appendix c : pmbus command details ot_fault_response the ot_fault_response command instructs the device on what action to take in response to a power stage over - temperature fault. the data byte is in the format given in table 28. the device also: ? sets the temperature bit in the status_ byte ? sets the overtemperature fault bit in the status_ temperature command, and ? notifies the host by asserting alert pin, unless masked. this condition is detected by the adc so the response time may be up to 100ms, typical. this command has one data byte. ut_fault_response the ut_fault_response command instructs the device on what action to take in response to a power stage under - temperature fault. the data byte is in the format given in table 28. the device also: ? sets the temperature bit in the status_ byte ? sets the undertemperature fault bit in the status_ temperature command, and ? notifies the host by asserting alert pin, unless masked. this condition is detected by the adc so the response time may be up to 100ms, typical. this command has one data byte. table 28. data byte contents: ton_max_fault_response, vin_ov_fault_response, ot_fault_response, ut_fault_response bits description value meaning 7:6 response for all values of bits [7:6], the ltm4675: ? sets the corresponding fault bit in the status commands, and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_ faults command ? the output is commanded through the runn pin, the operation command, or the combined action of the runn pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltm4675 00 the pmbus device continues operation without interruption. 01 not supported. writing this value will generate a cml fault. 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000-110 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off ( by the runn pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_ retry_ delay command. 2:0 delay time xxx not supported. values ignored ltm 4675 4675f
106 for more information www.linear.com/ltm4675 appendix c : pmbus command details fault sharing fault sharing propagation command name cmd code description type paged d ata format units nvm default value mfr_gpio_ propagate n 0xd2 configuration that determines which faults are propagated to the gpio pins. r/w word y reg y 0x6893 mfr_gpio_ propagate the mfr_gpio_ propagate command enables the faults that can cause the gpio n pin to assert low. the command is formatted as shown in table 29. faults can only be propagated to the gpio if they are programmed to respond to faults. this command has two data bytes. table 29. gpio n propagate fault configuration. the gpio 0 and gpio 1 pins are designed to provide electrical notification of selected events to the user. some of these events are common to both output channels. others are specific to an output channel. they can also be used to share faults between channels. bit(s) symbol operation b[15] vout disabled while not decayed. this is used in a polyphase configuration when bit 0 of the mfr_chan_config is a zero. if the channel is turned off, by toggling the run pin or commanding the part off, and then the run is reasserted or the part is commanded back on before the output has decayed, vout will not restart until the 12.5% decay is honored. the gpio pin is asserted during this condition if bit 15 is asserted. b[14] mfr_gpio_ propagate_short_cmd_cycle 0: no action 1: asserts low if commanded off then on before the output has sequenced off. re-asserts high 120ms after sequence off. b[13] mfr_gpio_propagate_ton_max_fault 0: no action if a ton_max_ fault fault is asserted 1: associated output will be asserted low if a ton_max_ fault fault is asserted gpio0 is associated with page 0 ton_max_ fault faults gpio1 is associated with page 1 ton_max_ fault faults b[12] mfr_gpio0_propagate_vout_uvuf, mfr_gpio1_propagate_vout_uvuf unfiltered vout_uv_fault_limit comparator output gpio0 is associated with channel 0 gpio1 is associated with channel 1 b[11] mfr_gpio0_propagate_int_ot, mfr_gpio1_propagate_int_ot 0: no action if the mfr_ot_fault_limit fault is asserted 1: associated output will be asserted low if the mfr_ ot_fault_limit fault is asserted b[10] mfr_pwrgd1_en* 0: no action if channel 1 power_good is not true 1: associated output will be asserted low if channel 1 power_good is not true if this bit is asserted, the gpio_fault_response must be ignore. if the gpio_fault_ response is not set to ignore, the part will latch off and never be able to start. b[9] mfr_pwrgd 0_en* 0: no action if channel 0 power_good is not true 1: associated output will be asserted low if channel 0 power_good is not true if this bit is asserted, the gpio_fault_response must be ignore. if the gpio_fault_ response is not set to ignore, the part will latch off and never be able to start. b[8] mfr_gpio0_propagate_ut, mfr_gpio1_propagate_ut 0: no action if the ut_fault_limit fault is asserted 1: associated output will be asserted low if the ut_fault_limit fault is asserted gpio0 is associated with page 0 ut faults gpio1 is associated with page 1 ut faults ltm 4675 4675f
107 for more information www.linear.com/ltm4675 appendix c : pmbus command details fault sharing response command name cmd code description type paged d ata format units nvm default value mfr_gpio_response 0xd5 action to be taken by the device when the gpio pin is asserted low. r/w byte y reg y 0xc0 mfr_gpio_response this command determines the controllers response to the gpion pin being pulled low by an external source. value meaning 0xc0 gpio_inhibit the ltm4675 will three-state the output in response to the gpio pin pulled low. 0x00 gpio_ignore the ltm4675 continues operation without interruption. the device also: ? sets the none_of_the_above bit in the status_ byte ? sets the mfr bit in the status_word ? sets the gpiob bit in the status_mfr_specific command, and ? notifies the host by asserting alert pin, unless masked. the alert pin pulled low can be disabled by setting bit[1] of mfr_chan_cfg. this command has one data byte. table 29. gpio n propagate fault configuration. the gpio 0 and gpio 1 pins are designed to provide electrical notification of selected events to the user. some of these events are common to both output channels. others are specific to an output channel. they can also be used to share faults between channels. bit(s) symbol operation b[7] mfr_gpio0_propagate_ot, mfr_gpio1_propagate_ot 0: no action if the ot_ fault_limit fault is asserted 1: associated output will be asserted low if the ot_fault_limit fault is asserted gpio0 is associated with page 0 ot faults gpio1 is associated with page 1 ot faults b[6] reserved b[5] reserved b[4] mfr_gpio0_propagate_input_ov, mfr_gpio1_propagate_input_ov 0: no action if the vin_ov_fault_limit fault is asserted 1: associated output will be asserted low if the vin_ov _fault_limit fault is asserted b[3] reserved b[2] mfr_gpio0_propagate_iout_oc, mfr_gpio1_propagate_iout_oc 0: no action if the iout_oc_fault_limit fault is asserted 1: associated output will be asserted low if the iout_oc_fault_limit fault is asserted gpio0 is associated with page 0 oc faults gpio1 is associated with page 1 oc faults b[1] mfr_gpio0_propagate_vout_uv, mfr_gpio1_propagate_vout_ uv 0: no action if the vout_uv_fault_limit fault is asserted 1: associated output will be asserted low if the vout_uv_fault_limit fault is asserted gpio0 is associated with page 0 uv faults gpio1 is associated with page 1 uv faults b[0] mfr_gpio0_propagate_vout_ov, mfr_gpio1_propagate_vout_ov 0: no action if the vout_ov_fault_limit fault is asserted 1: associated output will be asserted low if the vout_ov_fault_limit fault is asserted gpio0 is associated with page 0 ov faults gpio1 is associated with page 1 ov faults *the pwrgd status is designed as an indicator and not to be used for power supply sequencing. ltm 4675 4675f
108 for more information www.linear.com/ltm4675 appendix c : pmbus command details scratchpad command name cmd code description type paged d ata format units nvm default value user_data_00 0xb0 oem reserved. typically used for part serialization. r/w word n reg y na user_data_01 0xb1 manufacturer reserved for ltpowerplay. r/w word y reg y na user_data_02 0xb2 oem reserved. typically used for part serialization. r/w word n reg y na user_data_03 0xb3 a nvm word available for the user. r/w word y reg y 0x0000 user_data_04 0xb4 a nvm word available for the user. r/w word n reg y 0x0000 user_data _00 through user_data_04 these commands are non-volatile memory locations for customer storage. the customer has the option to write any value to the user_data_nn at any time. however, the ltpowerplay software and contract manufacturers use some of these commands for inventory control. modifying the reserved user_data_nn commands may lead to undesirable inventory control and incompatibility with these products. these commands have 2 data bytes and are in register format. identification command name cmd code description type paged d ata format units nvm default value pmbus_revision 0x98 pmbus revision supported by this device. current revision is 1.2. r byte n reg 0x22 capability 0x19 summary of pmbus optional communication protocols supported by this device. r byte n reg 0xb0 mfr_id 0x99 the manufacturer id of the ltm4675 in ascii. r string n asc lt c mfr_model 0x9a manufacturer part number in ascii. r string n asc ltm4675 mfr_serial 0x9e serial number of this specific unit in ascii. r block n cf na mfr_special_id 0xe7 manufacturer code representing the ltm4675. r word n reg 0x47ax pmbus_revision the pmbus_revision command indicates the revision of the pmbus to which the device is compliant. the ltm4675 is pmbus version 1.2 compliant in both part i and part ii. this read-only command has one data byte. capability this command provides a way for a host system to determine some key capabilities of a pmbus device. the ltm4675 supports packet error checking, 400khz bus speeds, and alert pin. this read-only command has one data byte. mfr_id the mfr_id command indicates the manufacturer id of the ltm4675 using ascii characters. this read-only command is in block format. ltm 4675 4675f
109 for more information www.linear.com/ltm4675 appendix c : pmbus command details mfr_model the mfr_model command indicates the manufacturers part number of the ltm4675 using ascii characters. this read-only command is in block format. mfr_serial the mfr_serial command contains up to 9 bytes of custom formatted data used to uniquely identify the ltm4675 configuration. this read-only command is in block format. mfr_special_id the 16-bit word representing the part name. the 0x47e prefix denotes the part is an ltm4675, x is adjustable by the manufacturer. this read-only command has 2 data bytes. fault warning and status command name cmd code description type paged format units nvm default value clear_ faults 0x03 clear any fault bits that have been set. send byte n na smbalert_mask 0x1b mask alert activity. block r/w y reg y see cmd details mfr_clear_peaks 0xe3 clears all peaks values. send byte n na status_ byte 0x78 one byte summary of the units fault condition. r/w byte y reg na status_word 0x79 tw o byte summary of the units fault condition. r/w word y reg na status_vout 0x7a output voltage fault and warning status. r/w byte y reg na status_iout 0x7b output current fault and warning status. r/w byte y reg na status_input 0x7c input supply (sv in ) fault and warning status. r/w byte n reg na status_ temperature 0x7d tsns na -sensed fault and warning status for read_temerature_1. r/w byte y reg na status_cml 0x7e communication and memory fault and warning status. r/w byte n reg na status_mfr_ specific 0x80 manufacturer specific fault and state information. r/w byte y reg na mfr_ pads 0xe5 digital status of the i/o pads. r word n reg na mfr_common 0xef manufacturer status bits that are common across multiple lt c ics/modules. r byte n reg na clear_ faults the clear_faults command is used to clear any fault bits that have been set. this command clears all bits in all status commands simultaneously. at the same time, the device negates (clears, releases) its alert pin signal output if the device is asserting the alert pin signal. if the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the alert pin low. clear_ faults can take up to 10s to process. if a fault occurs within that time frame it may be cleared before the status register is set. this write-only command has no data bytes. ltm 4675 4675f
110 for more information www.linear.com/ltm4675 appendix c : pmbus command details the clear_ faults does not cause a unit that has latched off for a fault condition to restart. units that have shut down for a fault condition are restarted when: ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? mfr_reset or restore_user_all command is issued. ? bias power is removed and reapplied to the integrated circuit mfr_clear_peaks the mfr_clear_peaks command clears the mfr_*_peak data values. a mfr_reset or restore_user_all will initiate this command. this write-only command has no data bytes. smbalert_mask the smbalert_mask command can be used to prevent a particular status bit or bits from asserting alert as they are asserted. figure 57 shows an example of the write word format used to set an alert mask, in this case without pec. the bits in the mask byte align with bits in the specified status register. for example, if the status_temperature command code is sent in the first data byte, and the mask byte contains 0x40, then a subsequent external overtemperature warning would still set bit 6 of status_temperature but not assert alert. all other supported status_ temperature bits would continue to assert alert if set. figure 58 shows an example of the block write C block read process call protocol used to read back the present state of any supported status register, again without pec. smbalert _ mask cannot be applied to status _ byte , status _ word , mfr _ common or mfr _ pads . factory default masking for applicable status registers is shown below. providing an unsupported command code to smbalert_mask will generate a cml for invalid/unsupported data. figure 57. example of setting smbalert_mask figure 58. example of reading smbalert_mask p 1 slave address smbalert_mask command code status_x command code w a a s 7 8 8 1 8 1 1 1 1 1 a a mask byte 4675 f57 slave address smbalert_mask command code block count (= 1) w a a s 7 8 8 1 status_x command code 8 1 1 1 1 1 a a ? sr 1 block count (= 1) a na p 4675 f58 a 8 8 1 1 1 1 mask byte slave address 7 r 1 ltm 4675 4675f
111 for more information www.linear.com/ltm4675 appendix c : pmbus command details smbalert_mask default setting: (refer also to summary of the status registers, figure 59) status resister alert mask value masked bits status_vout n 0x00 none status_iout n 0x00 none status_ temperature n 0x00 none status_cml 0x00 none status_input 0x00 none status_mfr_specific n 0x11 bit 4 (internal pll unlocked), bit 0 (gpio n pulled low by external device) status_byte the status_ byte command returns a one-byte summary of the most critical faults. status_ byte message contents: bit status bit name meaning 7 busy a fault was declared because the ltm4675 was unable to respond. 6 off this bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. 5 vout_ov an output overvoltage fault has occurred. 4 iout_oc an output overcurrent fault has occurred. 3 vin_uv not supported (ltm4675 returns 0). 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory or logic fault has occurred. 0 none of the above a fault not listed in bits[7:1] has occurred. this command has one data byte any supported fault bit in this command will initiate an alert event. status_word the status_word command returns a two-byte summary of the channels fault condition. the low byte of the status_word is the same as the status_ byte command. status_word high byte message contents: bit status bit name meaning 15 v out an output voltage fault or warning has occurred. 14 i out an output current fault or warning has occurred. 13 input an sv in input voltage fault or warning has occurred. 12 mfr_specific a fault or warning specific to the ltm4675 has occurred. 11 power_good# the power_good state is false if this bit is set. 10 fans not supported (ltm4675 returns 0). 9 other not supported (ltm4675 returns 0). 8 unknown not supported (ltm4675 returns 0). any supported fault bit in this command will initiate an alert event. this command has two data bytes. ltm 4675 4675f
112 for more information www.linear.com/ltm4675 appendix c : pmbus command details status_vout the status_vout command returns one byte of v out status information. status_vout message contents: bit meaning 7 v out overvoltage fault. 6 v out overvoltage warning. 5 v out undervoltage warning. 4 v out undervoltage fault. 3 vout_max warning. 2 ton_max fault. 1 toff_max warning. 0 not supported by the ltm4675 (returns 0). alert can be asserted if any of bits[7:1] are set. these may be cleared by writing a 1 to their bit position in status_vout, in lieu of a clear _ faults command. this command has one data byte. status_iout the status_iout command returns one byte of i out status information. status_iout message contents: bit meaning 7 i out overcurrent fault. 6 not supported (ltm4675 returns 0). 5 i out overcurrent warning. 4:0 not supported (ltm4675 returns 0). alert can be asserted if any supported bits are set. any supported bit may be cleared by writing a 1 to that bit position in status_iout, in lieu of a clear_ faults command. this command has one data byte. status_input the status_input command returns one byte of v in (sv in ) status information. status_input message contents: bit meaning 7 sv in overvoltage fault. 6 not supported (ltm4675 returns 0). 5 sv in undervoltage warning. 4 not supported (ltm4675 returns 0). 3 unit off for insufficient sv in voltage. 2 not supported (ltm4675 returns 0). 1 input over current warning. 0 not supported (ltm4675 returns 0) alert can be asserted if bit 7 is set. bit 7 may be cleared by writing it to a 1, in lieu of a clear_ faults command. this command has one data byte. ltm 4675 4675f
113 for more information www.linear.com/ltm4675 appendix c : pmbus command details status_ temperature the status_ temperature command returns one byte of sensed power stage temperature status information. status_ temperature message contents: bit meaning 7 external overtemperature fault. 6 external overtemperature warning. 5 not supported (ltm4675 returns 0). 4 external undertemperature fault. 3:0 not supported (ltm4675 returns 0). alert can be asserted if any supported bits are set. any supported bit may be cleared by writing a 1 to that bit position in status_temperature, in lieu of a clear_ faults command. this command has one data byte. status_cml the status_cml command returns one byte of status information on received commands, internal memory and logic. status_cml message contents: bit meaning 7 invalid or unsupported command received. 6 invalid or unsupported data received. 5 packet error check failed. 4 memory fault detected. 3 processor fault detected. 2 reserved (ltm4675 returns 0). 1 other communication fault. 0 other memory or logic fault. alert can be asserted if any supported bits are set. any supported bit may be cleared by writing a 1 to that bit position in status_cml, in lieu of a clear_ faults command. this command has one data byte. status_mfr_specific the status_mfr_specific commands returns one byte with the manufacturer specific status information. each channel has a copy of the same information. only bit 0 is page specific. the format for this byte is: bit meaning 7 internal temperature fault limit exceeded. 6 internal temperature warn limit exceeded. 5 nvm crc fault. 4 pll is unlocked 3 fault log present 2 v dd33 uv or ov fault 0 gpio pin asserted low by external device (paged) ltm 4675 4675f
114 for more information www.linear.com/ltm4675 appendix c : pmbus command details if any of these bits are set, the mfr bit in the status_word will be set. the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. exception: the fault log present bit can only be cleared by issuing the mfr_fault_log_clear command. any supported fault bit in this command will initiate an alert event. this command has one data byte. mfr_ pads this command provides the user a means of directly reading the digital status of the i/o pins of the device. the bit assignments of this command are as follows: bit assigned digital pin 15 v dd33 ov fault 14 v dd33 uv fault 13 reserved 12 reserved 11 adc values invalid, occurs during start-up 10 sync output disabled due to external clock 9 powergood1 8 powergood0 7 device driving run 1 low 6 device driving run 0 low 5 run 1 4 run 0 3 device driving gpio1 low 2 device driving gpio0 low 1 gpio1 0 gpio0 a 1 indicates the condition is true. this read-only command has two data bytes. mfr_common the mfr_common command contains bits that are common to all lt c digital power and telemetry products. bit meaning 7 module not driving alert low 6 module not busy 5 calculations not pending 4 output not in transition 3 nvm initialized 2 reserved 1 share_clk timeout 0 wp pin status this read-only command has one data byte. ltm 4675 4675f
115 for more information www.linear.com/ltm4675 appendix c : pmbus command details (paged) mfr_pads 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vdd33 0v vdd33 uv (reads 0) (reads 0) invalid adc result(s) sync output disabled externally channel 1 is power_good channel 0 is power_good ltm4675 forcing run1 low ltm4675 forcing run0 low run1 pin state run0 pin state ltm4675 forcing gpio1 low ltm4675 forcing gpio0 low gpio1 pin state gpio0 pin state status_mfr_specific 7 6 5 4 3 2 1 0 (paged) 4675 f59 status_input 7 6 5 4 3 2 1 0 status_word status_byte 7 6 5 4 3 2 1 0 (paged) mfr_common 7 6 5 4 3 2 1 0 module not driving alert low module not busy internal calculations not pending output not in transition eeprom initialized (reads 0) share_clk_low wp pin high status_temperature 7 6 5 4 3 2 1 0 status_cml 7 6 5 4 3 2 1 0 status_vout* 7 6 5 4 3 2 1 0 (paged) status_iout 7 6 5 4 3 2 1 0 (paged) maskable description general fault or warning event dynamic status derived from other bits yes no no generates alert yes no not directly bit clearable yes no no vout_ov fault vout_ov warning vout_uv warning vout_uv fault vout_max warning ton_max fault toff_max warning (reads 0) iout_oc fault (reads 0) iout_oc warning (reads 0) (reads 0) (reads 0) (reads 0) (reads 0) ot fault ot warning (reads 0) ut fault (reads 0) (reads 0) (reads 0) (reads 0) invalid/unsupported command invalid/unsupported data packet error check failed memory fault detected processor fault detected (reads 0) other communication fault other memory or logic fault internal temperature fault internal temperature warning eeprom crc error internal pll unlocked fault log present (reads 0) vout short cycled gpio pulled low by external device vin_ov fault sv in (reads 0) vin_uv warning sv in (reads 0) unit off for insuffcient sv in voltage (reads 0) iin_oc warning (reads 0) 15 14 13 12 11 10 9 8 vout iout input mfr_specific power_good# (reads 0) (reads 0) (reads 0) busy off vout_ov iout_oc (reads 0) temperature cml none of the above figure 59. summary of the status registers ltm 4675 4675f
116 for more information www.linear.com/ltm4675 appendix c : pmbus command details telemetry command name cmd code description type paged format units nvm default value read_vin 0x88 measured input supply (sv in ) voltage. r word n l11 v na read_vout 0x8b measured output voltage. r word y l16 v na read_iin 0x89 calculated input supply current. r word n l11 a na mfr_read_iin 0xed calculated input current per channel. r word y l11 a na read_iout 0x8c measured output current. r word y l11 a na read_ temperature_1 0x8d power stage temperature sensor. this is the value used for all temperature related processing, including iout_cal_gain. r word y l11 c na read_temperature_2 0x8e control ic die temperature. does not affect any other registers. r word n l11 c na read_duty_cycle 0x94 duty cycle of the top gate control signal. r word y l11 % na read_pout 0x96 calculated output power . r word y l11 w na mfr_vout_peak 0xdd maximum measured value of read_vout since last mfr_clear_peaks. r word y l16 v na mfr_vin_peak 0xde maximum measured value of read_vin since last mfr_clear_peaks. r word n l11 v na mfr_temperature_1_peak 0xdf maximum measured value of power stage temperature (read_temperature_1) since last mfr_clear_peaks. r word y l11 c na mfr_temperature_2_peak 0xf 4 maximum measured value of control ic die temperature (read_temperature_2) since last mfr_clear_peaks. r word n l11 c na mfr_iout_peak 0xd7 report the maximum measured value of read_iout since last mfr_clear_peaks. r word y l11 a na mfr_adc_control 0xd8 adc telemetry parameter selected for repeated fast adc read back. r/w byte n reg 0x00 mfr_adc_telemetry_ status 0xda adc telemetry status indicating which parameter is most recently converted when the short round robin adc loop is enabled r/w byte n reg na read_vin the read_vin command returns the measured sv in input voltage, in volts. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_vout the read_vout command returns the measured output voltage in the same format as set by the vout_mode command. this read-only command has two data bytes and is formatted in linear_16u format. read_iin the read_iin command returns the input current in amperes. note: input current is calculated from read_iout current and the read_duty_cycle value from both outputs plus the mfr_iin_offset. for accurate values at low currents the part must be in continuous conduction mode. the greatest source of error if dcr sensing is used, is the accuracy of the inductor parasitic dc resistance (dcr) at room temperature iout_cal_gain. read_iin = mfr_read_iin_ page0 + mfr_read_iin_ page 1 ltm 4675 4675f
117 for more information www.linear.com/ltm4675 appendix c : pmbus command details this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_read_iin the mfr_read_iin command is a paged reading of the input current that applies the paged mfr_iin_offset parameter. this calculation is similar to read_iin except the paged values are used. mfr_read_iin = mfr_iin_offset + (iout ? duty_ cycle) this command has 2 data bytes and is formatted in linear_5s_11s format. read_iout the read_iout command returns the average output current in amperes. the iout value is a function of: a) the differential voltage measured across the i sense pins b) the iout_cal_gain value c) the mfr_iout_cal_gain_tc value, and d) read_temperature_1 value e) the mfr_temp_1_gain and the mfr_temp_1_offset this read-only command has two data bytes and is formatted in linear_5s_11s format. read_temperature_1 the read_temperature_1 command returns the temperature, in degrees celsius, of the external sense element. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_temperature_2 the read_temperature_2 command returns the temperature, in degrees celsius, of the internal sense element. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_duty_cycle the read_duty_cycle command returns the duty cycle of controller, in percent. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_pout the read_pout command is a paged reading of the dc/dc converter output power in watts . the pout is calculated based on the most recent correlated output voltage and current readings. this command has 2 data bytes and is formatted in linear_5s_11s format. mfr_vout_peak the mfr_vout_peak command reports the highest voltage, in volts, reported by the read_vout measurement. this command is cleared using the mfr_clear_peaks command. this read -only command has two data bytes and is formatted in linear_16u format. ltm 4675 4675f
118 for more information www.linear.com/ltm4675 appendix c : pmbus command details mfr_vin_peak the mfr_vin_peak command reports the highest voltage, in volts, reported by the read_vin measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_temperature_1_peak the mfr_temperature_1_peak command reports the highest temperature, in degrees celsius, reported by the read_temperature_1 measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_temperature_2_peak the mfr_temperature_2_peak command reports the highest temperature, in degrees celsius, reported by the read_temperature_2 measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_iout_peak the mfr_ iout_ peak command reports the highest current, in amperes, reported by the read_ iout measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_adc_control the mfr_ adc_ control command determines the adc read back selection. a default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of 100ms. the user can command a non- zero value to monitored a single parameter with an approximate update rate of 8 ms. this command has a latency of up to two adc conversions or approximately 16ms ( power stage temperature conversions may have a latency of up to three adc conversion or approximately 24ms). selecting a value of 0 x 0 d will enable a short round robin loop. this commanded value runs a short telemetry loop only selecting vout0, iout0, vout1 and iout1 in a round robin manner. the round robin typical latency is 27ms. it is recommended the part remain in standard telemetry mode except for special cases where fast adc updates of a single parameter is required. the part should be commanded to monitor the desired parameter for a limited period of time ( say, less than a second) then set the com- mand back to standard round robin mode. if this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage servoing is disabled. when round robin is reasserted, all warnings and faults and servo mode are re- enabled. ltm 4675 4675f
119 for more information www.linear.com/ltm4675 appendix c : pmbus command details commanded value telemetry selected 0x00 standard adc round robin telemetry 0x01 sv in 0x02 reserved 0x03 reserved 0x04 internal ic temperature 0x05 channel 0 vout 0x06 channel 0 iout 0x07 reserved 0x08 channel 0 power stage-sensed temperature 0x09 channel 1 vout 0x0a channel 1 iout 0x0b reserved 0x0c channel 1 power stage or tsns 1a -sensed temperature 0x0d adc short round robin 0x0e-0xff reserved if a reserved command value is entered, the part will default to internal ic temperature and issue a cml[6] fault. cml[6] faults will continue to be issued by the ltm4675 until a valid command value is entered. this read/write command has 1 data byte and is formatted in register format. mfr_adc_telemetry_ status the mfr_adc_telemetry_status command provides the user the means to determine the most recent adc conversion when the mfr_adc_control short round robin loop is enabled using command 0xd8 value 0x0d. the bit assignments of this command are as follows: bit telemetry d ata available 7 reserved returns 0 6 reserved returns 0 5 reserved returns 0 4 reserved returns 0 3 channel 1 i out readback (i out1 ) 2 channel 1 v out readback (v out1 ) 1 channel 0 i out readback (i out0 ) 0 channel 0 v out readback (v out0 ) write to mfr_adc_telemetry_ status with data bits set to 1 clear the respective bits. this read/write command has 1 data byte and is formatted in register format. nvm (eeprom) memory commands store/restore command name cmd code description type paged format units nvm default value store_user_all 0x15 store user operating memory to eeprom. send byte n na restore_user_all 0x16 restore user operating memory from eeprom. identical to mfr_reset. send byte n na mfr_compare_user_all 0xf0 compares current command contents with nvm. send byte n na ltm 4675 4675f
120 for more information www.linear.com/ltm4675 appendix c : pmbus command details store_user_all the store_user_all command instructs the pmbus device to copy the non-volatile user contents of the operating memory to the matching locations in the non-volatile user nvm memory (eeprom). the 10 year data retention can only be guaranteed when store_user_all is executed at 0c t j 85 c. executing this command at junction temperatures above 85c or below 0c is not recommended because data retention cannot be guaranteed for that condition. if the die temperature exceeds 130c, the store_user_all command is disabled. the command is re-enabled when the ic temperature drops below 125c. communication with the ltm4675 and programming of the eeprom can be initiated when vdd33 is available and sv in is not applied. to enable the part in this state, using global address 0x5b write 0x2b followed by 0xc4. the part can now be communicated with, and the project file updated. to write the updated project file to the eeprom issue a store_user_all command. when sv in is applied, a mfr_reset or restore_user_all must be issued to allow the pwm to be enabled and valid adcs to be read. this write-only command has no data bytes. restore_user_all the restore_user_all command provides an alternate means by which the user can perform a mfr_reset of the ltm4675. this write-only command has no data bytes. mfr_compare_user_all the mfr_compare_user_all command instructs the pmbus device to compare current command contents with what is stored in non-volatile memory . if the compare operation detects differences, a cml bit 0 fault will be generated. mfr_compare_user_all commands are disabled if the die exceeds 130c and are not re-enabled until the die temperature drops below 125c. this write-only command has no data bytes. fault logging command name cmd code description type paged d ata format units nvm default value mfr_fault_log 0xee fault log data bytes. this sequentially retrieved data is used to assemble a complete fault log. r block n cf y na mfr_fault_log_ store 0xea command a transfer of the fault log from ram to eeprom. send byte n na mfr_fault_log_clear 0xec initialize the eeprom block reserved for fault logging. send byte n na mfr_fault_ log the mfr_ fault_ log command allows the user to read the contents of the fault_ log after the first fault occurrence since the last mfr_ fault_ log_ clear command was last written. the contents of this command are stored in non- volatile memory, and are cleared by the mfr_ fault_ log_ clear command. the length and content of this command are listed in table 30. if the user accesses the mfr_ fault_ log command and no fault log is present, the command will return a data length of 0. if a fault log is present, the mfr_ fautl_ log will always return a block of data 147 bytes long. if a fault occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data. ltm 4675 4675f
121 for more information www.linear.com/ltm4675 appendix c : pmbus command details note: the approximate transfer time for this command is 3.4ms using a 400khz clock. this read-only command is in block format. mfr_fault_log_store the mfr_fault_log_store command forces the fault log operation to be written to eeprom just as if a fault event occurred. this command will generate a mfr_specific fault if the enable fault logging bit is set in the mfr_ config_all command. if the die temperature exceeds 130c, the mfr_fault_log_store command is disabled until the ic temperature drops below 125c. up-time counter is in the fault log header. the counter is the time since the last module reset (mfr_reset, restore_user_all, or sv in - power cycle) in 200s increments. this is a 48-bit binary counter. this write-only command has no data bytes. table 30. fault logging. this table outlines the format of the block data from a read block data of the mfr_fault_log command. data format definitions lin 11 = pmbus = rev 1.2, part 2, section 7.1 lin 16 = pmbus rev 1.2, part 2, section 8. mantissa portion only byte = 8 bits interpreted per definition of this command d ata bits d ata format byte num block read command block length byte 147 the mfr_fault_log command is a fixed length of 147 bytes the block length will be zero if a data log event has not been captured header information fault log preface [7:0] asc 0 returns ltxx beginning at byte 0 if a partial or complete fault log exists. word xx is a factory identifier that may vary part to part. [7:0] 1 [15:8] reg 2 [7:0] 3 fault source [7:0] reg 4 refer to table 31. mfr_real_time [7:0] reg 5 48 bit share-clock counter value when fault occurred (200s resolution). [15:8] 6 [23:16] 7 [31:24] 8 [39:32] 9 [47:40] 10 mfr_vout_peak ( page 0) [15:8] l16 11 peak read_vout on channel 0 since last power-on or clear_peaks command. [7:0] 12 mfr_vout_peak ( page 1) [15:8] l16 13 peak read_vout on channel 1 since last power-on or clear_peaks command. [7:0] 14 mfr_iout_peak ( page 0) [15:8] l11 15 peak read_iout on channel 0 since last power-on or clear_peaks command. [7:0] 16 ltm 4675 4675f
122 for more information www.linear.com/ltm4675 appendix c : pmbus command details table 30. fault logging. this table outlines the format of the block data from a read block data of the mfr_fault_log command. mfr_iout_peak ( page 1) [15:8] l11 17 peak read_iout on channel 1 since last power-on or clear_peaks command. [7:0] 18 mfr_vin_peak [15:8] l11 19 peak read_vin since last power-on or clear_peaks command. [7:0] 20 read_ temperature1 ( page 0) [15:8] l11 21 channel 0 power stage during last event. [7:0] 22 read_ temperature1 ( page 1) [15:8] l11 23 channel 1 power stage or tsns 1a -sensed temperature 1 during last event. [7:0] 24 read_ temperature2 [15:8] l11 25 internal temperature sensor during last event. [7:0] 26 cyclical d ata event n (data at which fault occurred; most recent data) event n represents one complete cycle of adc reads through the mux at time of fault. example: if the fault occurs when the adc is processing step 15, it will continue to take readings through step 25 and then store the header and all 6 event pages to eeprom read_vout ( page 0) [15:8] lin 16 27 [7:0] lin 16 28 read_vout ( page 1) [15:8] lin 16 29 [7:0] lin 16 30 read_iout ( page 0) [15:8] lin 11 31 [7:0] lin 11 32 read_iout ( page 1) [15:8] lin 11 33 [7:0] lin 11 34 read_vin [15:8] lin 11 35 [7:0] lin 11 36 read_iin [15:8] lin 11 37 [7:0] lin 11 38 status_vout ( page 0) byte 39 status_vout ( page 1) byte 40 status_word ( page 0) [15:8] word 41 [7:0] word 42 status_word ( page 1) [15:8] word 43 [7:0] word 44 status_mfr_specific ( page 0) byte 45 status_mfr_specific ( page 1) byte 46 event n-1 (data measured before fault was detected) read_vout ( page 0) [15:8] lin 16 47 [7:0] lin 16 48 read_vout ( page 1) [15:8] lin 16 49 [7:0] lin 16 50 read_iout ( page 0) [15:8] lin 11 51 [7:0] lin 11 52 ltm 4675 4675f
123 for more information www.linear.com/ltm4675 appendix c : pmbus command details table 30. fault logging. this table outlines the format of the block data from a read block data of the mfr_fault_log command. read_iout ( page 1) [15:8] lin 11 53 [7:0] lin 11 54 read_vin [15:8] lin 11 55 [7:0] lin 11 56 read_iin [15:8] lin 11 57 [7:0] lin 11 58 status_vout ( page 0) byte 59 status_vout ( page 1) byte 60 status_word ( page 0) [15:8] word 61 [7:0] word 62 status_word ( page 1) [15:8] word 63 [7:0] word 64 status_mfr_specific ( page 0) byte 65 status_mfr _specific ( page 1) byte 66 * * * event n-5 (oldest recorded data) read_vout ( page 0) [15:8] lin 16 127 [7:0] lin 16 128 read_vout ( page 1) [15:8] lin 16 129 [7:0] lin 16 130 read_iout ( page 0) [15:8] lin 11 131 [7:0] lin 11 132 read_iout ( page 1) [15:8] lin 11 133 [7:0] lin 11 134 read_vin [15:8] lin 11 135 [7:0] lin 11 136 read_iin [15:8] lin 11 137 [7:0] lin 11 138 status_vout ( page 0) byte 139 status_vout ( page 1) byte 140 status_word ( page 0) [15:8] word 141 [7:0] word 142 status_word ( page 1) [15:8] word 143 [7:0] word 144 status_mfr_specific ( page 0) byte 145 status_mfr_specific ( page 1) byte 146 ltm 4675 4675f
124 for more information www.linear.com/ltm4675 appendix c : pmbus command details mfr_fault_log_clear the mfr_fault_log_clear command will erase the fault log file stored values. it will also clear bit 3 in the status_mfr_specific command. after a clear is issued, the status can take up to 8ms to clear. this write-only command is send bytes. block memory write/read command name cmd code description type paged d ata format units nvm default value mfr_ee_unlock 0xbd unlock user eeprom for access by mfr_ee_erase and mfr_ee_ data commands. r/w byte n reg na mfr_ee_erase 0xbe initialize user eeprom for bulk programming by mfr_ee_ data . r/w byte n reg na mfr_ee_ data 0xbf data transferred to and from eeprom using sequential pmbus word reads or writes. supports bulk programming. r/w word n reg na all the (eeprom) commands are disabled if the die temperature exceeds 130c. (eeprom) commands are re-enabled when the die temperature drops below 125c. mfr_ee_xxxx mfr_ee_xxxx commands are used to facilitate bulk programming of the internal eeprom. contact the factory for more details. table 31. explanation of position_fault values position_ fault value source of fault log 0xff mfr_fault_log_store 0x00 ton_max_ fault channel 0 0x01 vout_ov_ fault channel 0 0x02 vout_uv_ fault channel 0 0x03 iout_oc_ fault channel 0 0x05 ot_ fault channel 0 0x06 ut_ fault channel 0 0x07 vin_ov_ fault channel 0 0x0a mfr_ot_ fault channel 0 0x10 ton_max_ fault channel 1 0x11 vout_ov_ fault channel 1 0x12 vout_uv_ fault channel 1 0x13 iout_oc_ fault channel 1 0x15 ot_ fault channel 1 0x16 ut_ fault channel 1 0x17 vin_ov_ fault channel 1 0x1a mfr_ot_ fault channel 1 ltm 4675 4675f
125 for more information www.linear.com/ltm4675 package description package row and column labeling m ay vary among module products. review each package layout carefully. table 32. ltm4675 bga pinout pin id function pin id function pin id function pin id function pin id function pin id function a1 v out0 b1 v out0 c1 v out0 d1 v out0 e1 gnd f1 gnd a2 gnd b2 gnd c2 gnd d2 gnd e2 gpio 0 f2 gpio 1 a3 gnd b3 gnd c3 tsns 0 d3 tsns 0 e3 alert f3 run 0 a4 gnd b4 gnd c4 gnd d4 sda e4 scl f4 run 1 a5 gnd b5 gnd c5 gnd d5 gnd e5 sync f5 sgnd a6 gnd b6 gnd c6 gnd d6 comp 0b e6 comp 0a f6 sgnd a7 gnd b7 gnd c7 gnd d7 v osns0+ e7 v osns0- f7 intv cc a8 gnd b8 sw 0 c8 gnd d8 v orb0+ e8 v orb0- f8 gnd a9 v in0 b9 v in0 c9 v in0 d9 v in0 e9 gnd f9 sv in pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 gnd j1 v out1 k1 v out1 l1 v out1 m1 v out1 g2 asel h2 f swphcfg j2 gnd k2 gnd l2 gnd m2 gnd g3 v out0cfg h3 v trim0cfg j3 t sns1a k3 tsns 1b l3 gnd m3 gnd g4 v out1cfg h4 v trim1cfg j4 v dd25 k4 wp l4 gnd m4 gnd g5 sgnd h5 share_clk j5 v dd33 k5 gnd l5 gnd m5 gnd g6 sgnd h6 comp 1a j6 comp 1b k6 gnd l6 gnd m6 gnd g7 intv cc h7 v osns1 j7 v orb1 k7 gnd l7 gnd m7 gnd g8 gnd h8 gnd j8 gnd k8 gnd l8 sw 1 m8 gnd g9 gnd h9 gnd j9 v in1 k9 v in1 l9 v in1 m9 v in1 ltm 4675 4675f
126 for more information www.linear.com/ltm4675 package description package photograph 1 2 3 4 5 6 7 top view 8 9 m l k j h g f e d c b a v out0 v out0 f swphcfg gpio 0 gpio 1 v in0 v in0 gnd gnd gnd sw 0 gnd tsns 0 tsns 0 run0 alert gnd comp 0b v osns0 + v orb0 ? sv in v orb0 + v osns0 ? comp 0a sync sda scl run 1 sgnd intv cc gnd gnd gnd asel v out0cfg v trim0cfg v trim1cfg share_clk comp 1a v osns1 v out1cfg gnd gnd gnd v out1 tsns 1a tsns 1b wp sw 1 v dd25 v dd33 comp 1b v orb1 v out1 v in1 v in1 ltm 4675 4675f
127 for more information www.linear.com/ltm4675 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. bga package 108-lead (16mm 11.9mm 3.51mm) (reference ltc dwg # 05-08-1931 rev a) package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view 3 see notes d e b e e b f g detail a pin 1 9 8 7 6 5 4 3 2 1 a b c d e f g h k j l m suggested pcb layout top view 0.000 0.0000 0.630 0.025 ? 108x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 5.080 5.080 3.810 3.810 2.540 2.540 1.270 1.270 6.9850 detail a ?b (108 places) a detail b package side view z m x yzddd m zeee a2 detail b substrate a1 b1 ccc z mold cap symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 3.31 0.50 2.81 0.60 0.60 0.36 2.45 nom 3.51 0.60 2.91 0.75 0.63 16.00 11.90 1.27 13.97 10.16 0.41 2.50 max 3.71 0.70 3.01 0.90 0.66 0.46 2.55 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 108 // bbb z z h2 h1 notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature bga 108 1212 rev a tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes ltm 4675 4675f
128 for more information www.linear.com/ltm4675 ? linear technology corporation 2015 lt 0515 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltm4675 related parts typical application v out1 , 1.8v adjustable up to 9a c inh 22f 3 c inl 220f 10k 9 v in 5.75v to 17v pwm clock synch. time base synch. slave address = 1001111_r/w (0x4f) switching frequency: 500khz no gui configuration and no part specific programming required in multi-module systems, configuring rail_address is recommended c out0 100f 4 c out1 100f 4 v out0 , 1.0v adjustable up to 9a v in0 v in1 sv in v dd33 load 0 scl sda alert run 0 run 1 gpio 0 gpio 1 sync share_clk asel f swphcfg v out0cfg v trim0cfg v out1cfg v trim1cfg intv cc v dd25 sw 0 sw 1 comp 0a comp 0b comp 1a comp 1b gnd wp 6.34k 1% 50ppm/c ltm4675 4676a f60 + smbus interface with pmbus command set on/off control, fault management, power sequencing load 1 v out0 tsns 0 v orb0 + v osns0 + v osns0 ? v orb0 ? v orb1 v out1 tsns 1a tsns 1b v osns1 sgnd design resources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power search parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. part number description comments ltm4620a dual 13a or single 26a step-down module regulator 4.5v v in 16v, 0.6v v out 5.3v, 15mm 15mm 4.41mm lga ltm4630 dual 18a or single 36a step-down module regulator 4.5v v in 15v, 0.6v v out 1.8v, 16mm 16mm 4.41mm lga ltm4676a dual 13a or single 26a step-down module regulator with digital power system management 4.5v v in 17v , 0.5v v out 5.5v, 16mm 16mm 5.01mm bga ltc3880/ltc3883 dual and single output dc/dc controllers with power system management 0.5% tue 16-bit adc, voltage/current/ temperature monitoring and supervision ltc2977/ltc2974 8- and 4-channel pmbus power system managers 0.25% tue 16-bit adc, voltage/ temperature monitoring and supervision licensed under u.s. patent 7000125 and other related patents worldwide. tue is total unadjusted error. figure 60. 9a, 1v and 9a, 1.8 v output dc/dc module regulator with serial interface ltm 4675 4675f

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